Search

Presents information on an article which reported variations of the leakage current density of capacitors after annealing. Experimental procedures; Results and discussion; Conclusion.

Pt or Arsenic (As)-doped polycrystalline-silicon (poly-Si) gate/HfO2 or HfO2-Al2O3/p-type Si metal oxide semiconductor (MOS) capacitors were fabricated using an atomic-layer-deposition technique, and their compatibility with poly-Si gate was investigated using a comparison with the Pt gate. The HfO2-Al2O3 stack film was found to have better As diffusion-blocking properties as a result of the rather thick amorphous interlace layer including Al2O2 than that of the HfO2 film. N+ duped poly-Si gate/HfO2-Al2O3 MOS capacitors had a lower current density of - 1.1 × 10-9 A/cm² at - 1 V resulting in a small hysteresis voltage due to the lower As penetration and thick amophous interface layer. These results suggest that N+ doped poly-Si gate/HfO2-Al2O3, MOS capacitors are compatible with the poly-Si gate, which is also comparable to the Pt gate. [ABSTRACT FROM AUTHOR]

This study investigated the variations in the dielectric constant with film thickness and measurement temperature of (Ba0.48Sr0.52)TiO3 thin-film capacitors with thicknesses ranging from 65 to 273 nm. The films were prepared by an on-axis rf magnetron sputtering, having Pt top and bottom electrodes. The thicker film showed a higher dielectric constant with a larger temperature dependence of the dielectric constant, and the maximum dielectric constant was observed at a higher temperature. The thickness-dependent dielectric constant at a given measurement temperature was explained by using the previously reported interfacial capacitance model, containing the intrinsic dead layer and electrode polarization. The temperature-dependent dielectric property could be explained using a modified Curie-Weiss (C-W) behavior of the film taking the nonferroelectric interfacial capacitance components into consideration. However, the C-W constant and Curie temperature of the ferroelectric layer must be modified in order to obtain a reasonable interfacial layer thickness. [ABSTRACT FROM AUTHOR]

The ferroelectric negative capacitance (NC) draws a great deal of attention for low‐power negative capacitance field‐effect transistors (NCFET) and NC capacitors. The fabrication of steep‐slope FET (subthreshold swing < 60mVdec−1) is reported, followed by modeling approaches. While the device fabrication favors a ferroelectric gate structure without interlayer metal, many NCFET models adopt interlayer metal between the ferroelectric layer and metal–insulator–semiconductor structure. The metal interlayer averages out spatial variation in the ferroelectric polarization, enabling a compact charge‐based relation between the layers. In addition, the approach assumes that the NC effect emerges from the ferroelectric layer regardless of the metal interlayer, which is not necessarily probable. This work reinvestigates the possible NC effect in ferroelectric–dielectric capacitors connected by a metal interlayer. The experiment confirms that the NC effect in the metal–ferroelectric–dielectric–metal structure does not appear in the metal–ferroelectric–metal–dielectric–metal structure. These results are inconsistent with the multidomain‐1D Landau–Ginzburg‐Devonshire model. In contrast, the suppression of the NC effect in the structure is fully explained by the advanced inhomogeneous stray‐field energy model, which simulates the dynamic evolution of polarization and screening charges. Therefore, an NCFET with a metal interlayer is impractical. [ABSTRACT FROM AUTHOR]

The electric-field-induced rejuvenation behavior of the degraded ferroelectric properties of integrated Pt/SrBi[sub 2]Ti[sub 2]O[sub 9]/Pt capacitors was investigated. Integration processes, especially plasma-enhanced chemical vapor deposition of the passivation layers, generate hydrogen ions and electrons which act as domain pinning centers and a source of a negative internal electric field. Domain pinning was found to reduce the remanent polarization (P[sub r]) and internal field that induces an imprint to the positive bias direction. Alternating current cyclings with peak voltages of +/-6 V rejuvenated the degraded ferroelectric performance of the capacitors. Cycling with a negative bias was more effective in fixing the damage than was a positive bias. Baking at 125 °C again degraded the rejuvenated ferroelectric performance. The degree of re-degradation was also dependent on the polarity of the rejuvenating bias. The polarity-dependent behavior of rejuvenation was explained on the basis of a negative-internal-field model due to preferential capture of electrons from the plasma at the top electrodes. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) on Ta-doped SnO 2 thin films is proposed as a methodology for the fabrication of capacitor electrodes, for application in dynamic random-access memories (DRAMs). In ALD of doped materials, dopant concentration gradients inevitably occur due to the cyclic process-based characteristics of ALD. In this study, the dopant distribution improves drastically by the decrease in the growth per cycle of TaO x ALD. The modified ALD recipe exploits the low reactivity between Ta and Sn precursors to facilitate a reduction in the growth per cycle. The Ta-doped SnO 2 films grown based on this modified ALD recipe exhibit improved crystallinity and conductivity. The ALD process yields excellent conformality of the Ta-doped SnO 2 film over a hole structure with a high aspect ratio of ~10, both in terms of physical thickness and composition. Additionally, the Ta-doped SnO 2 films serve as a template for the overgrowing dielectric TiO 2 film, which induces the formation of a high-temperature phase with a high dielectric constant, rutile TiO 2 , and exhibit excellent thermal stability even after annealing at 400 °C in forming gas atmosphere. These findings demonstrate that the proposed methodology for the growth of Ta-doped SnO 2 can facilitate the fabrication of capacitor electrodes for application in DRAMs. Unlabelled Image • A new ALD process of Ta-doped SnO 2 films is demonstrated. • Potential applications include use as reduction-resistant capacitor electrode. • Dopant distribution improves by decrease in the growth per cycle of TaO x ALD. • Films reveal ease of formation of high-k rutile TiO 2 and excellent thermal stability. [ABSTRACT FROM AUTHOR]

This study examined the imprint mechanism of a ferroelectric Pt/Pb(Zr,Ti)O3(150-nm-thick)/Pt capacitor using pulse switching transient current measurements. The progression of the imprint was well explained by the propagation of a localized charge injection area, where there was an increase in coercive voltage and interfacial capacitance over the entire capacitor area. The as-received samples exhibited uniform interfacial capacitance over the total area. Charge injection resulted in a more rectified remanent polarization–applied voltage relationship compared with the as-received sample. Analytic functional forms for the switching charge and local switching area were also derived. [ABSTRACT FROM AUTHOR]

An efficient computational method is proposed within a first-principles framework to calculate capacitances of metal-insulator-metal structures including interfacial effects. In this approach, we employ metal-insulator models under external electric fields to calculate dielectric responses near the interface region. Macroscopically averaged potentials allow for evaluating the capacitance and local dielectric constants of the corresponding metal-insulator-metal capacitor. We apply this method to calculate the capacitance of Au/MgO(100)/Au and Ni/ZrO2(110)/Ni with dielectric thicknesses of nanometers. While the Au/MgO interface is relatively free of interfacial effects, the computational results for Ni/ZrO2 indicate the presence of interfacial regions with dielectric constants noticeably lower than that of the bulk. Microscopic origins are discussed. [ABSTRACT FROM AUTHOR]

SrTiO 3 (STO) thin films, grown by atomic layer deposition (ALD), were studied for capacitors in dynamic random access memory. The STO ALD process consisted of two steps: the growth of seed layer followed by a rapid thermal annealing (RTA) process at 650 °C to crystallize it, and the deposition of the main layer on top of the seed layer at 370 °C to induce the in-situ crystallization. During single cooling process after the RTA of the seed layer, voids and nano-cracks were formed due to the thermal expansion mismatch between STO film and Si substrate. This problem was well mitigated by adopting the stepwise cooling process, wherein the holding time of 30 s at 500, 350, and 200 °C suppressed the defect formation in the seed layer. Therefore, the main layer grown on that seed layer showed an improved microstructure with a high bulk dielectric constant of 135. However, the increase in total annealing time degraded the interface quality between the STO and the bottom electrode, which finally worsened the insulating property. As a result, the minimum equivalent oxide thicknesses with low leakage current densities (< 10 − 7 A/cm 2 at 0.8 V) for the single and stepwise cooling processes were 0.39 nm and 0.46 nm, respectively. [ABSTRACT FROM AUTHOR]

The effect of the top electrode (TE) on the ferroelectric properties and switching endurance of thin Hf0.5Zr0.5O2 films was examined. The TiN/Hf0.5Zr0.5O2/TiN capacitor can endure electric cycling up to 109 times, which is promising for the next‐generation memory. RuO2 TE was reduced during annealing due to the reactive TiN bottom electrode, resulting in the degradation of the ferroelectric properties and endurance. In addition, the endurance of the TiN/Hf0.5Zr0.5O2/TiN capacitors was optimized by changing the film thickness and the postannealing temperature. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim) Part of Focus Issue on “Functional Oxides” (Eds.: T. Frauenheim, J. M. Knaup, P. Broqvist, S. Ramanathan) The TiN/Hf0.5Zr0.5O2/TiN capacitor can endure up to 109 times the electric cycling, which is promising for the next‐generation memory. RuO2 top electrode was reduced during annealing due to the reactive TiN bottom electrode, resulting in the degradation of the ferroelectric properties and endurance. The endurance of the TiN/Hf0.5Zr0.5O2/TiN capacitors is optimized by changing the film thickness and the post‐annealing temperature. [ABSTRACT FROM AUTHOR]

Abstract: Metal-insulator-semiconductor capacitors were fabricated with sputtered ZnO and atomic layer deposited HfO2 as the semiconductor and gate dielectric layers, respectively. From the capacitance–voltage measurements, it was confirmed that pre-deposition annealing of the sputtered ZnO layer at 300°C in air greatly decreased the interfacial trap density (∼2×1012 cm−2 eV−1). X-ray photoelectron spectroscopy showed a decrease in the OH bonds adsorbed on the ZnO surface after pre-deposition annealing, which improved the interface property. A very small capacitance equivalent thickness of 1.3nm was achieved, which decreased the operation voltage (<5V) of the device significantly. [Copyright &y& Elsevier]

Abstract: In this work, we have prepared metal–insulator–metal capacitors for dynamic random access memory capacitor application using atomic layer deposition of TiO2 high-κ dielectric and RuO2 bottom electrode. We compare TiO2 layers grown using TiCl4 precursor or Ti-tetra-isopropoxide precursor, and Al-doped TiO2 layers grown using Ti-tetra-isopropoxide precursor. The capacitors were analyzed in the terms of capacitance – voltage and current – voltage measurements and transmission electron microscopy imaging. [Copyright &y& Elsevier]

The filamentary resistance switching mechanism of a Pt/40 nm TiO2/Pt capacitor structure in voltage sweep mode was investigated. It was unambiguously found that the conducting filaments propagate from the cathode interface and that the resistance switching is induced by the rupture and recovery of the filaments in the localized region (3–10 nm thick) near the anode. The electrical conduction behavior in the high resistance state was well explained by the space charge limited current (SCLC) mechanism that occurs in the filament-free region. The various parameters extracted from the SCLC fitting supported the localized rupture and formation of filaments near the anode. [ABSTRACT FROM AUTHOR]

The minority carrier (electron) capture process and the interface trap density of a TiN/Al[sub 2]O[sub 3]/p-Si metal-oxide-semiconductor capacitor were examined by deep level transient spectroscopy (DLTS). It was found that the activation energies of the large peaks detected at higher temperatures with gate bias voltages of 1.8, 1.5, 1.3, and 1.1 V were 0.19, 0.24, 0.29, and 0.37 eV, respectively. These energies were related to the electron-capture process from the conduction band by interface states in the upper half of the Si band gap. The interface state passivation effect of postannealing in a hydrogen ambient was studied from the minority carrier capture process and the usual DLTS signals. The D[sub it] at an energy of 0.35 eV from the valence bandedge decreased from 1 × 10[sup 12] cm[sup -2] eV[sup -1] at the as-fabricated state to 4 × 10[sup 11] cm[sup -2] eV[sup - 1] after H[sub 2] annealing at 450 °C. It was also found that the D[sub it] at an energy of 0.3 eV from the conduction bandedge decreased to the same amount by the same annealing process. [ABSTRACT FROM AUTHOR]

The film thickness-dependent imprinting behavior (voltage shift) of (Pb, La)(Zr, Ti)O[sub 3] capacitors was evaluated by a thermal stress process under a remanence bias. The remanent polarization (P[sub r]) was found to be almost independent of the film thickness whereas in the 50-300 nm range the relative dielectric constant (ε[sub r]) increased linearly with the square root of the film thickness. It was found that the voltage shift, which was attributed to the accumulation of charged defects near the electrode interface, also increased linearly with increasing film thickness. In addition, the charge accumulated thickness varied with the square root of the film thickness. This was established from a simple assumption that the level of charge accumulation is determined by the product of the total amount of charged defects (total film thicknessxcharged defect density) and the internal field that is generated by the P[sub r]. Therefore, the imprint is much more a bulk-related degradation phenomenon compared to the fatigue. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]

The electrical characteristics of metal–insulator–metal (MIM) capacitors consisting of a ZrO2/Al2O3/ZrO2 (ZAZ) dielectric film, a TiN bottom electrode (BE), and two different top electrodes (TEs; TiN and Ru) are examined. The enhanced property in the leakage current density versus equivalent oxide thickness (J–tox) plot is observed in the MIM structure with the Ru TE for the ZAZ film with specific film thickness of ≈4.6 nm. Especially, the J due to the electron injection from the TiN BE was significantly decreased for the Ru TE case compared to the TiN TE sample at 1–2 MV cm−1 electric field region. These extraordinary behaviors are found to have originated the change in the oxygen vacancy density in the ZAZ film, which induces Poole–Frenkel emission through the reaction with the active oxygen during the Ru TE fabrication process. The difference in nonlinearity of the capacitance–voltage (C–V) curve also indicates a different trap density at the interface of ZAZ and the TiN BE, suggesting a change in the oxygen vacancy density in the ZAZ film. Two different materials, sputter‐grown TiN and atomic layer deposition (ALD)‐grown Ru, are prepared for the top electrode (TE) material of ZrO2/Al2O3/ZrO2 (ZAZ)‐based capacitors for DRAM application. The electrical characteristics are investigated, and the capacitor with a Ru TE shows a much lower J value than the TiN TE at an oxide thickness (tox) value of about 1.0 nm. [ABSTRACT FROM AUTHOR]

Voltage offset in the polarization-voltage characteristics of Pb(Zr,Ti)O[sub 3] (PZT) capacitors was evaluated by a thermal stress process. A thermally induced voltage shift occurs when heating the sample under either remanence or a saturating bias. It was found that the voltage shifts can, to a large extent, be attributed to the role of charged defects and the defect-dipole alignment throughout the films. PZT film with a high Zr/Ti ratio, i.e., rhombohedral compositions exhibited the best imprint resistance. When these films were doped wit up to 6% La, the imprint resistance was further improved. It was also found that B-site donors were more effective in minimizing the voltage shift than A-site donors. However, dopants with the same charge value as Pb, for example, Ca and Sr, did not affect the thermally induced voltage shifts of the films since they could not reduce the charged defects in the films. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

The degradation behavior of integrated Pt/SrBi[sub 2]Ta[sub 2]O[sub 9]/Pt capacitors by hydrogen impregnation during the intermetal dielectric deposition and passivation is investigated. The hydrogen ions generated as a reaction byproduct from the SiH[sub 4]-based deposition processes of the dielectric films induce reduction in the remanent polarization (P[sub r]) as well as the imprint behavior of the small size capacitors (2x2 μm[sup 2]). The degree of degradation is quite dependent on the size of the individual capacitors. The smaller capacitors underwent more serious degradation implying that the hydrogen ions impregnate into the SBT layer mainly along the etched side area of the capacitors not through the top Pt electrode. Metallization adopting TiN/Al/TiN/Ti multilayer is very effective in suppressing the hydrogen impregnation. In particular, the Ti layer appears to block the hydrogen penetration. Therefore, the optimized metallization scheme, wider metal lines than the top electrode area by 1 μm, successfully protects the integrated capacitors from the hydrogen damage. 12 μC/cm2 of 2P[sub r] and 1.1 V of 2V[sub c] (coercive voltage) with an imprinting voltage of 0.16 V were obtained from the passivated 2x2 μm[sup 2] array capacitors by the optimized metallization. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]