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Ferroelectric (FE)-HfO2-based FETs (FEFETs) are one of the most promising candidates for emerging memories. However, the FE material suffers from a unique reliability phenomenon known as imprint: the coercive voltage shifts during data retention, which has been regarded as a major issue for memory operation, while the mechanism causing it is still under research. In this article, imprint and its recovery in FE-HfO2 are investigated in detail by comprehensive electrical measurements to reveal its underlying mechanism including the cause of asymmetric coercive voltage shifts. The recovery measurements clarify that domain switching is indispensable for the recovery from imprint. The subloop imprint effect shows that imprint and its recovery must be independent for each domain. In addition, switching time measurements and corresponding fitting results with the nucleation-limited-switching (NLS) model strongly indicate that imprint is caused by domain-seeds-pinning. Based on these results, we conclude that charge trapping and detrapping affecting activation barriers for domain switching, accompanied by domain switching, is responsible for imprint and its recovery. [ABSTRACT FROM AUTHOR]

In this work, the physical and electrical properties of SrxTi1-xOy (STO)-based metal-insulator-metal capacitors (MIMcaps) with various compositions are studied in detail. While most recent studies on STO were done on noblelike metal electrodes (Ru, Pt), this work focuses on a low temperature (250 °C) atomic layer deposition (ALD) process, using an alternative precursor set and carefully optimized processing conditions, enabling the use of low-cost, manufacturable-friendly TiN electrodes. Physical analyses show that the film crystallization temperature, its texture and morphology strongly depends on the Sr/Ti ratio. Such physical variations have a direct impact on the electric properties of SrxTi1-xOy based capacitors. It is found that Sr-enrichment result in a monotonous decrease in the dielectric constant and leakage current as predicted by ab initio calculations. The intercept of the EOT vs physical thickness plot further indicates that increasing the Sr-content at the film interface with the bottom TiN would result in lower interfacial equivalent-oxide thickness. [ABSTRACT FROM AUTHOR]

We investigate bias temperature instability (BTI) charge trapping trends in high- $k$ metal gate (HKMG) stacks with a variety of work function metals (WFMs). Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work function. However, experimental data on capacitors show enhanced or reduced charge trapping at a constant oxide electric field for different WFM stacks. We ascribe this to a different chemical interaction of the metals with the dielectric, which yields different defect profiles depending on the process thermal budget, and not to the gate work function per se. This observation is confirmed by comparing BTI degradation in nMOS and pMOS replacement gate planar transistors with three selected WFM stacks (representative of high-, standard-, and low- $V_{\mathrm{ th}}$ device flavors), and two different process thermal budgets. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy,” we also show that, on top of the unavoidable chemical interaction of different metals with the underlying SiO2/HfO2 dielectric stack, different gate work functions within a typical range of relevance (4.35–4.75 eV) can yield a different charge state of the deep high- $k$ defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs. [ABSTRACT FROM AUTHOR]

The electrical properties of Ru/SrTiO x /Ru capacitors have been investigated. Equivalent Oxide Thickness (EOT) of 0.38 nm at 0 V and current density of 10 −7 A cm −2 at ±1 V and 25 °C meet the sub-20 nm DRAM requirements. Relaxation measurements were performed, indicating acceptable charge loss. Modeling of charge trapping at defect sites based on multi-phonon trap-assisted-tunneling quantitatively well describes leakage and capacitance behavior. [ABSTRACT FROM AUTHOR]

Effective electron tunneling mass mtunnel is extracted from trap-assisted leakage in Sr-rich strontium titanate and rutile titanium oxide films in metal-insulator-metal (MIM) capacitors and compared with theoretical values obtained from first principles calculations of the imaginary band structure. Optimum orientations of films and stoichiometry impacting mtunnel are also discussed. Because future vertical DRAM integration schemes also stipulate maximum thickness of the MIM capacitor, mtunnel is shown to be a critical parameter influencing intrinsic leakage and potentially limiting further scaling. [ABSTRACT FROM AUTHOR]

Metal-insulator-metal capacitors with SrxTiyOz (STO) dielectric films on TiN, Ru, and RuOx bottom electrodes with TiN top electrodes were studied. Metastable perovskite STO films with compositions in the Sr/(Sr+Ti)∼54-64 at. % range were obtained by crystallization at 600 °C in N2 of dielectric stacks grown by atomic layer deposition consisting of Sr-rich STO films [Sr/(Sr+Ti)∼64 at. %] on thin interfacial TiOx layers. The significant decrease in equivalent oxide thickness (EOT) and STO lattice parameter observed with increasing TiOx thickness indicates full intermixing of the TiOx and STO layers during the crystallization anneal, which results in the formation of an STO layer with higher Ti content and higher dielectric constant. The Sr-rich STO on TiOx stacks crystallize with small grain size, favorable for low leakage (JG). A significant improvement in JG for e-injection from the bottom electrode is obtained when using RuOx, as compared to TiN or Ru. A milder JG improvement with RuOx bottom electrode is also seen for e-injection from the top TiN electrode, indicating that higher quality perovskite STO films are formed on RuOx, or equivalently, that their trap density is lower. We propose oxygen scavenging from the STO by TiN or Ru electrodes, eliminated or reversed when using RuOx, as an explanation for the improvement. Using an optimized RuOx/TiOx/STO/TiN stack we obtained leakage of 10-7 A/cm2 (at 0.8 V) and 0.4 nm EOT. [ABSTRACT FROM AUTHOR]

Metastable perovskite SrxTiyOz (STO) films were formed over a wide composition range by crystallization of layers grown by atomic layer deposition. An expansion of the lattice, decrease in permittivity and mild increase in band gap are observed with increasing Sr content. Sr-rich films [Sr/(Sr+Ti)∼62 at. %] show significant improvement in leakage current at low equivalent oxide thicknesses (EOT) as compared to stoichiometric films (Sr/(Sr+Ti) ∼50 at. %). TiN/STO/TiN capacitors with leakage ∼10-6 A/cm2 at 1 V were obtained at 0.6 nm EOT for crystalline Sr-rich STO. The difference in leakage behavior was found to correlate with different microstructures developed during crystallization. [ABSTRACT FROM AUTHOR]

We present direct physical evidence supporting the mechanisms we proposed to explain low leakage (Jg) and low equivalent oxide thickness (EOT) in RuOx/TiOx/Sr-rich SrxTiyOz(STO)/TiN metal-insulator-metal capacitors which achieve Jg = 10-7 A/cm2 (1 V) at 0.45 nm EOT: (1) healing of STO traps by O incorporation from RuOx during STO crystallization anneal for low leakage and (2) TiOx/Sr-rich STO intermixing during STO crystallization anneal resulting in a higher Ti-content, higher k-value STO layer for low EOT. Proof of oxygen incorporation into the STO layer from the RuOx electrode as well as of TiOx/STO intermixing were obtained by secondary ion mass spectrometry performed on samples fabricated using O18 for Ru oxidation. We also show excellent match between measured leakage vs. voltage and simulations of trap-assisted leakage with asymmetric trap profiles due to STO trap healing next to RuOx, further supporting our model. [ABSTRACT FROM AUTHOR]

The impact of different Ru precursors and/or deposition methods on the electrical characteristics of Ru/SrTiO x /Ru capacitors has been investigated. The observed increase of the leakage current density ( J g ) and the equivalent oxide thickness (EOT) for ALD (atomic layer deposition) deposited Ru layers compared to PVD (physical vapor deposition) deposited ones was found to be caused by a SrRuTiO x layer formation at the SrTiO x /Ru interface aided by the presence of the oxygen co-reactant used during the ALD, regardless of the precursor used. [ABSTRACT FROM AUTHOR]

Abstract: The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9–30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (>6eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal–insulator–metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3nm) drives the research towards dielectrics with k-values >50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr- and Ba-based perovskites, with SrTiO3 as one of the most promising candidates, as well as tantalates, titanates and niobates. [Copyright &y& Elsevier]

Abstract: A first-principles Density Functional Theory (DFT) approach was employed to predict the effective charges, phonon modes, band-gap and dielectric constant of a series of Sr-rich SrTiO3. The fabricated MIM capacitors confirm the theoretical trends obtained for the dielectric constants, the later showing a possible upper limit of the dielectric response. [Copyright &y& Elsevier]