Search

Semiconducting single‐walled carbon nanotube (CNT) is a promising candidate as a channel material for advanced logic transistors, attributed to the ultra‐thin 1‐nm cylindrical geometry, high mobility, and high carrier injection velocity. However, the presence of undesired CNT bundles in the CNT arrays for wafer‐scale device fabrication, even when utilizing the state‐of‐the‐art dimension‐limited self‐alignment (DLSA) method, poses challenges. These CNT bundles degrade the transistor gate's efficiency in controlling the flow of charge carriers in the CNT channel, leading to pronounced device‐to‐device variability. Here, a novel method is introduced to alleviate bundling in CNT arrays assembled via DLSA, by involving small molecule additive to screen the attractive van der Waals force between neighboring CNTs during the DLSA process, resulting in over 50% reduction in CNT bundling. Furthermore, a pioneering methodology for quantifying CNT bundles is presented and employed experimentally to assess bundles in dense CNT arrays assembled by DLSA using transmission electron microscopy. Both experimental data and molecular dynamics simulation reveal that CNT bundling originates from van der Waals attraction between CNTs, and the disturbed liquid‐liquid interface by accumulating excess polar molecules. These findings illuminate new pathways for realizing dense, bundle‐free CNT arrays. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) have great potential for future high-performance and energy-efficient transistor technology. To realize this potential, methods to dope the CNTs need to be developed to achieve low parasitic resistance of the transistor. Two key issues present themselves: (a) understanding the doping mechanism of the various methods and (b) stability of the doping method. For instance, although studies on molybdenum oxide (MoOx) demonstrate its ability to heavily dope nanomaterials, the interaction between MoOx and the CNT is unclear. Here, we observe an unstable effect of MoOx on the CNT and demonstrate dielectric passivation as a means to preserve the doping strength. The semiconducting CNTs exhibit greater than 103× reduction in resistance after stably doped with MoOx. By exploiting the instability of MoOx, we delve deeper into clarifying the doping mechanism. The relationship between the time-dependent material property of MoOx and the change in the electrical measurements of CNT devices is investigated to study the role of work function in doping the CNTs. We conclude that the doping mechanism of MoOx on the CNT is due to bandgap modulation by charge transfer, which occurs due to the difference in work function between MoOx and the CNT. [ABSTRACT FROM AUTHOR]

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2\times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions. [ABSTRACT FROM AUTHOR]

Carbon nanotube field effect transistors (CNFETs) have potential applications in future logic technology as they display good electrostatic control and excellent transport properties. However, contact resistance and leakage currents could limit scaling of CNFETs. Non-equilibrium Green’s function (NEGF) simulation investigates that coupling between contact metal and CNT impacts both contact resistance and leakage current. The physical mechanisms underlying the effects are analyzed. A model with calibrated metal coupling strength from experimental data projects ION-IOFF design space to understand the trade-off between shrinking contact and extension lengths. For CNT with diameter of 1 nm, both contact and extension lengths greater than 8 nm are a good compromise between ION and IOFF for digital logic in advanced technology nodes. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) transistors exemplify the fundamental tradeoff between desirable high mobility and undesirable leakage current due to the small effective mass and bandgap. To understand leakage current limits in high-speed CNT transistors, electrical bandgaps are extracted on 12 single-CNT top-gate MOSFETs from the energy gap between thermionic emission and band-to-band tunneling (BTBT) at 10 K. At 300 K the minimum IOFF at 0.5 V VDS is analyzed as a function of bandgap between 0.96 eV and 0.43 eV with IOFF-MINfrom 0.2 pA/CNT to 15 nA/CNT. NEGF simulation validates the bandgap extraction methodology and reproduces the experimental MOSFET IOFF-MIN data. A TCAD model calibrated to this work’s leakage data projects the accessible ION-IOFF design space bounded by CNT bandgap, indicating EG > 0.65 eV (dCNT < 1.3 nm) is needed to achieve 100 nA/ $\mu \text{m}$ at 0.5 V VDD and 250 CNT/ $\mu \text{m}$ for channel length above 20 nm. An EG of 1.06 eV (dCNT = 0.8 nm) can deliver $2750\times $ tunable range of IOFF by adjusting VT, which exceeds the $400\times $ tunable range of IOFF used in Si CMOS platform technologies. [ABSTRACT FROM AUTHOR]

We developed a fully analytical ballistic theory of carbon nanotube field effect transistors enabled by the development of an analytical surface potential capturing the temperature dependence and gate and quantum capacitance electrostatics. The analytical ballistic theory is compared to the experimental results of a ballistic transistor with good agreement. The validated analytical theory enables intuitive circuit design, provides techniques for parameter extraction of the bandgap and surface potential, and elucidates on the device physics of drain optical phonon scattering and its role in reducing the linear conductance and intrinsic gain of the transistor. Furthermore, a threshold voltage definition is proposed reflecting the bandgap-diameter dependence. Projections for key analog and digital performances are discussed. [ABSTRACT FROM AUTHOR]

A full-band analytical model of the equilibrium carrier density for single-wall semiconducting carbon nanotubes (sCNTs) is presented. The carrier density, which is a fundamental property of all semiconductors, is obtained using a semiempirical method for degenerate positions of the Fermi level and shows good agreement with numerical tight-binding results. The quantum capacitance is subsequently derived from the carrier density and used to develop a C-V model with good agreement with experimental quantum capacitance measurements. An analytical model of the gate coupling function of sCNTs is also reported which relates the internal surface potential with the external applied gate voltage. The diameter temperature and Fermi level dependency, and the essential properties of carbon nanotubes device physics are captured in these analytical equations. [ABSTRACT FROM AUTHOR]

The field of machine learning is witnessing rapid advances along several fronts: new machine learning models, new machine learning algorithms utilizing these models, new hardware architectures for these algorithms, and new technologies for creating energy-efficient implementations of such hardware architectures. Hyperdimensional (HD) computing represents one such model. Emerging nanotechnologies, such as carbon nanotube field-effect transistors (CNFETs), resistive random-access memory (RRAM), and their monolithic 3D integration, enable energy- and area-efficient hardware implementations of HD computing architectures. Such efficient implementations are achieved by exploiting several characteristics of the component nanotechnologies (e.g., energy-efficient logic circuits, dense memory, and incrementers naturally enabled by gradual reset of RRAM cells) and their monolithic 3D integration (enabling tight integration of logic and memory), as well as various characteristics of the HD computing model (e.g., embracing randomness that allows us to utilize rather than avoid inherent variations in RRAM and CNFETs, resilience to errors in the underlying hardware). We experimentally demonstrate and characterize an end-to-end HD computing nanosystem built using monolithic 3D integration of CNFETs and RRAM. Using our nanosystem, we experimentally demonstrate the pairwise classification of 21 languages with measured mean accuracy of up to 98% on >20 000 sentences (6.4 million characters), training using one text sample (~100 000 characters) per language, and resilient operation (98% accuracy) despite 78% of bits in HD representation being stuck at 0 or 1 in hardware. We also show that the monolithic 3D implementations of HD computing can have 35 $\times $ improved energy-execution time product for training and inference of language classification data sets (while using 3 $\times $ less area) compared to silicon CMOS implementations. [ABSTRACT FROM AUTHOR]

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1–7 pJ per bit and has a high programming endurance of up to 10^6\vphantom \sum ^R^R cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of <1~\mu \textA are achieved. [ABSTRACT FROM PUBLISHER]

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper, we present a framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that our framework: 1) runs over 100\boldsymbol \times faster than existing approaches and 2) accurately identifies the most important CNT processing parameters, together with CNFET circuit design parameters (e.g., for CNFET sizing and standard cell layouts), to minimize the impact of CNT variations on CNFET circuit speed with ≤5% energy cost, while simultaneously meeting circuit-level noise margin and yield constraints. [ABSTRACT FROM PUBLISHER]

Abstract: We report an effect in vertically-aligned carbon nanotube growth in which small catalyst features in proximity to large features show an enhanced growth rate. We apply this so-called “synergetic growth” effect in micrometer-scale patterns to produce vertical-like growth horizontally. This approach enables carbon nanotube integration into device applications requiring a fair degree of carbon nanotube alignment. The synergetic growth effect corroborates growth mechanisms describing carbon nanotube growth as a more complex process than elemental carbon supersaturating metal catalyst. [Copyright &y& Elsevier]

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems. [ABSTRACT FROM AUTHOR]

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 \mu\A and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology. [ABSTRACT FROM AUTHOR]

Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Today's CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) are promising candidates for transistors and interconnects for nanoelectronic circuits. Although CNTs intrinsically have excellent electrical conductivity, the large contact resistance at the interface between CNT and metal hinders its practical application. Here, we show that electrical contact to the CNT is substantially improved using a graphitic interfacial layer catalyzed by a Ni layer. The p-type semiconducting CNT with graphitic contact exhibits high on-state conductance at room temperature and a steep subthreshold swing in a back-gate configuration. We also show contact improvement to the semiconducting CNTs with different capping metals. To study the role of the graphitic interfacial layer in the contact stack, the capping metal and Ni catalyst were selectively removed and replaced with new metal pads deposited by evaporation and without further annealing. Good electrical contact to the semiconducting CNTs was still preserved after the new metal replacement, indicating that the contact improvement is attributed to the presence of the graphitic interfacial layer. [ABSTRACT FROM PUBLISHER]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

Historically, the off-state current Ioff and the supply voltage Vdd are specified as technology targets for Si metal–oxide–semiconductor field-effect transistors (MOSFETs) at each technology node. Emerging device technologies such as III–V transistors, carbon-nanotube FETs (CNFETs), and tunneling FETs (TFETs) are often targeted to outperform Si MOSFETs at the same Ioff and Vdd values. However, the conclusions from the conventional methodology are limited for advanced technology and diversified applications, when Dennard scaling is inefficient and different device structures are invented. We present a new device-technology assessment methodology based on energy–delay optimization, which takes into consideration key circuit-level information, such as logic depth, activity factors, and fanout (FO). Our methodology starts from device I– V and C –V characteristics and treat Ioff and Vdd as “free variables.” Together with device and supply-voltage variations, we obtain a corresponding and different optimal set of Ioff and Vdd and optimal energy–delay for each emerging device. We show that today's best available III–V transistors and CNFETs can outperform the best Si FETs by 1.5–2 and 2–3.5 times in terms of energy efficiency, respectively. Projected into the 10-nm-gate-length regime, III–V-on-insulator, CNFETs, and TFETs are 1.25, 2–3, and 5–10 times better than the International Technology Roadmap for Semiconductors target, for FO1 delays of 0.3, 0.1, and 1 ns, respectively. [ABSTRACT FROM PUBLISHER]

In this paper, an analytical model of intrinsic carbon-nanotube field-effect transistors is presented. The origins of the channel carriers are analyzed in the ballistic limit. A noniterative surface-potential model is developed based on an analytical electrostatic model and a piecewise constant quantum-capacitance model. The model is computationally efficient with no iteration or numerical integration involved, thus facilitating fast circuit simulation and system optimization. Essential physics such as drain-induced barrier lowering and quantum capacitance are captured with reasonable accuracy. [ABSTRACT FROM PUBLISHER]

Variations in the spatial density of carbon nanotubes (CNTs), resulting from the lack of precise control over CNT positioning during chemical synthesis, is a major hurdle to the scalability of carbon nanotube field effect transistor (CNFET) circuits. Such CNT density variations can lead to non-functional CNFET circuits. This paper presents a probabilistic framework for modeling the CNT count distribution contained in a CNFET of given width, and establishes the accuracy of the model using experimental data obtained from CNT growth. Using this model, we estimate the impact of CNT density variations on the yield of CNFET very large-scale integrated circuits. Our estimation results demonstrate that CNT density variations can significantly degrade the yield of CNFETs, and can be a major concern for scaled CNFET circuits. Finally, we analyze the impact of CNT correlation (i.e., correlation of CNT count between CNFETs) that exists in CNT growth, and demonstrate how the yield of a CNFET storage circuit (primarily limited by its noise immunity) can be significantly improved by taking advantage of such correlation. [ABSTRACT FROM PUBLISHER]

Carbon-based nanomaterials such as metallic single-walled carbon nanotubes, multiwalled carbon nanotubes (MWCNTs), and graphene have been considered as some of the most promising candidates for future interconnect technology because of their high current-carrying capacity and conductivity in the nanoscale, and immunity to electromigration, which has been a great challenge for scaling down the traditional copper interconnects. Therefore, studies on the performance and optimization of carbon-based interconnects working in a realistic operational environment are needed in order to advance the technology beyond the exploratory discovery phase. In this paper, we present the first demonstration of graphene interconnects monolithically integrated with industry-standard complementary metal–oxide–semiconductor technology, as well as the first experimental results that compare the performance of high-speed on-chip graphene and MWCNT interconnects. The graphene interconnects operate up to 1.3-GHz frequency, which is a speed that is commensurate with the fastest high-speed processor chips today. A low-swing signaling technique has been applied to improve the speed of carbon interconnects up to 30%. [ABSTRACT FROM PUBLISHER]

We present analyses for ACCNT (pronounced as “accent”), which is a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallic-nanotube tolerance, delivering high ON–OFF ratios while preserving current drive. We analyze the ACCNT methodology in terms of its tradeoffs and explore optimizations that may serve as future design guidelines. We also investigate circuit-level considerations and the impact of density variation on the ACCNT design. We find that ACCNT can improve the yield of a one-million transistor chip from 0% (conventional CNT design) up to 99% at a cost of \3.3\times area overhead if the fraction of semiconducting CNTs is improved to 99.9%. [ABSTRACT FROM PUBLISHER]

We demonstrate ACCNT (pronounced as "accent"), a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallic-nanotube tolerance, delivering high ON-OFF ratios (104-106) while preserving the current drive. In addition, this metallic-nanotube tolerance can be engineered arbitrarily close to 100%. We present the ACCNT concepts in detail, verifying the concepts and underlying assumptions via experimental results. We further demonstrate inverters using ACCNT and ACCNT scalability to a wafer scale. ACCNT marks the first demonstration of a VLSI-compatible metallic-nanotube-tolerant design methodology. [ABSTRACT FROM AUTHOR]

Due to their excellent electrical properties and small size, metallic carbon nanotubes (CNTs) are promising materials for interconnect wires in future integrated circuits. Indeed, simulations have firmly established CNTs as strong contenders for replacing or complementing copper interconnects. In this paper, we analyze the performances of a prototype 0.25-μm CMOS digital integrated circuit with select horizontal multiwall CNT (MWCNT) interconnects. Some local interconnect wires of the prototype chip were implemented, during a post-CMOS assembly process, by single 14-μm-long metallic MWCNT with 30-nm diameter, representative of future requirements for local interconnects. We evaluate the merits and challenges of MWCNT interconnects in a realistic silicon integrated-circuit environment. We experimentally extract the subnanosecond delays of these wires to quantitatively benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, as well as with the expected performances of scaled copper wires. Finally, we discuss the origin of the discrepancies between our experimental results and the modeling projections. [ABSTRACT FROM AUTHOR]

Carbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to silicon CMOS. Simulations show that CNFET inverters fabricated with a perfect CNFET technology have 13 times better energy delay product compared with 32-nm silicon CMOS inverters. The following two fundamental challenges prevent the fabrication of CNFET circuits with the aforementioned advantages: 1) misaligned and mispositioned CNTs and 2) metallic CNTs. Misaligned and mispositioned CNTs can cause incorrect functionality. This paper presents a technique for designing arbitrary logic functions using CNFET circuits that are guaranteed to implement correct functions even in the presence of a large number of misaligned and mispositioned CNTs. Experimental demonstration of misaligned and mispositioned CNT-immune logic structures is also presented. [ABSTRACT FROM AUTHOR]

This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic CV/I gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance. [ABSTRACT FROM AUTHOR]

This paper presents a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs). This model is valid for CNFET with a wide range of chiralities and diameters and for CNFET with either metallic or semiconducting carbon-nanotube (CNT) conducting channel. The modeled nonidealities include the quantum confinement effects on both circumferential and axial directions, the acoustical/optical phonon scattering in the channel region, and the screening effect by the parallel CNTs for CNFET with multiple CNTs. In order to be compatible with both large- (digital) and small-signal (analog) applications, a complete transcapacitance network is implemented to deliver the real-time dynamic response. This model is implemented with an HSPICE. Using this model, we project a 13 times CV/I improvement of the intrinsic CNFET with (19, 0) CNT over the bulk n-type MOSFET at the 32-nm node. The model described in this paper serves as a starting point toward the complete CNFET- device model incorporating the additional device/circuit-level nonidealities and multiple CNTs reported in the paper of Deng and Wong. [ABSTRACT FROM AUTHOR]

In this paper, we present an in-depth analysis of the nanowire and nanotube device performance under process variability. Although every process parameter variation drastically affects the conventional MOSFET performance, we found that nanowire/nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and geometric properties. It is observed that a two-input NAND gate with nanowire or nanotube FETs shows a more than four times less performance variation than its bulk MOSFET counterpart and about two times less than FinFET devices at the 45 and 32 nm technologies, respectively. In other words, nanowire/nanotube FETs will have a larger margin for process parameter variations than bulk and FinFET devices for an allowable performance variation limit. While it is evident that process variations are going to be a major limiting factor for conventional MOSFET devices in future generations, this analysis is expected to further encourage nanowire and nanotube research for high-performance circuit applications. [ABSTRACT FROM AUTHOR]

The theoretical performance of carbon nanotube field-effect transistors (CNFETs) with Schottky barriers (SBs) is examined by means of a general ballistic model. A novel approach is used to treat the SBs at the metal-nanotube contacts as mesoscopic scatterers by modifying the distribution functions for carriers in the channel. Noticeable current reduction is observed compared to previous ballistic models without SBs. Evanescent- mode analysis is used to derive a scale length and the potential profile near the contacts for radially symmetric CNFET structures. Band-to-band tunneling current and ambipolar conduction are also treated. The effects of different device geometries and different nanotube chiralities on the drain-current are studied using this simple model. Quantum conductance degradation due to SBs is also observed. [ABSTRACT FROM AUTHOR]

Semiconducting carbon nanotubes are robust molecules with nanometer-scale diameters that can be used in field-effect transistors, from larger thin-film implementation to devices that work in conjunction with silicon electronics, and can potentially be used as a platform for high-performance digital electronics as well as radio-frequency and sensing applications. Recent progress in the materials, devices, and technologies related to carbon nanotube transistors is briefly reviewed. Emphasis is placed on the most broadly impactful advancements that have evolved from single-nanotube devices to implementations with aligned nanotubes and even nanotube thin films. There are obstacles that remain to be addressed, including material synthesis and processing control, device structure design and transport considerations, and further integration demonstrations with improved reproducibility and reliability; however, the integration of more than 10,000 devices in single functional chips has already been realized. [ABSTRACT FROM AUTHOR]

In this paper, high-performance back-gated carbon nanotube field-effect transistors based on transferred aligned carbon nanotubes were fabricated and studies found that the on/off ratio can reach 107 and the current density can reach 1.6 μA/μm after electrical breakdown. In addition, chemical doping with hydrazine was used to convert the p-type aligned nanotube devices into n-type. These devices were further utilized to demonstrate various logic circuits, including p-type metal-oxide-semiconductor inverters, diode-loaded inverters, complementary metal-oxide-semiconductor inverters, NAND, and NOR gates. This approach could work as the platform for future nanotube-based nanoelectronics. [ABSTRACT FROM AUTHOR]

High-purity semiconducting single-walled carbon nanotubes (s-SWNTs) with little contamination are desired for high-performance electronic devices. Although conjugated polymer wrapping has been demonstrated as a powerful and scalable strategy for enriching s- SWNTs, this approach suffers from significant contaminations by polymer residues and high cost of conjugated polymers. Here, we present a simple but general approach using removable and recoverable conjugated polymers for separating s-SWNTs with little polymer contamination. A conjugated polymer with imine linkages was synthesized to demonstrate this concept. Moreover, the SWNTs used are without prepurifications and very low cost. The polymer exhibits strong dispersion for large-diameter s-SWNTs with high yield (23.7%) and high selectivity (99.7%). After s-SWNT separation, the polymer can be depolymerized into monomers and be cleanly removed under mild acidic conditions, yielding polymer-free s-SWNTs. The monomers can be almost quantitatively recovered to resynthesize polymer. This approach enables isolation of "clean" s- SWNTs and, at the same time, greatly lowers costs for SWNT separation. [ABSTRACT FROM AUTHOR]