Search

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

In this paper the electromigration (EM) limits of Cu nano-interconnects are studied considering the impact of microstructure in Co cap schemes and performance booster technologies i.e. via pre-fill and scaled barrier-liner schemes. A combination of experimental and physics-based modelling approaches is employed to provide fundamental understanding of the involved mechanisms. The results show that linewidth reduction, higher trench depth, i.e. larger aspect ratio (AR) and thinner barrier and liners result in more polycrystalline copper texture. It was found that at 10.5 nm linewidth, ~95% of the nano-interconnect length is polycrystalline while for 25 nm linewidth this is ~85%. A 90% drop of jfail i.e. the current density that induces failure at 10 years, was found by scaling linewidth from 25 nm to 10.5 nm in Cu interconnects with Co cap. Experiments show a 70% drop of time to failure due to barrier film thickness scaling from 3 nm to 2 nm for PVD TaN. Utilization of Co cap and via prefill were found to increase jfail by ~10 fold and ~3 fold, respectively.

Atomic layer deposition of ruthenium is studied as a barrierless metallization solution for future sub-10 nm interconnect technology nodes. We demonstrate the void-free filling in sub-10 nm wide single damascene lines using an ALD process in combination with 2.5 Å of ALD TiN interface and postdeposition annealing. At such small dimensions, the ruthenium effective resistance depends less on the scaling than that of Cu/barrier systems. Ruthenium effective resistance potentially crosses the Cu curve at 14 and 10 nm according to the semiempirical interconnect resistance model for advanced technology nodes. These extremely scaled ruthenium lines show excellent electromigration behavior. Time-dependent dielectric breakdown measurements reveal negligible ruthenium ion drift into low-κ dielectrics up to 200 °C, demonstrating that ruthenium can be used as a barrierless metallization in interconnects. These results indicate that ruthenium is highly promising as a replacement to Cu as the metallization solution for future technology nodes.

This article identifies four major reliability challenges related to TSV-based 3-D integrated circuits and their solutions that are being developed at imec.

We describe an X-ray diffraction imaging technique for nondestructive, in situ measurement of die warpage in encapsulated chip packages at acquisition speeds approaching real time. The results were validated on a series of samples with known inbuilt convex die warpage, and the measurement of wafer bow was compared with the results obtained by optical profilometry. We use the technique to demonstrate the impact of elevated temperature on a commercially sourced micro quad flat nonlead chip package and show that the strain becomes locked in at a temperature between 94 °C and 120 °C. Using synchrotron radiation at the Diamond Light Source, warpage maps for the entire $2.2~\textrm {mm} \times 2.4~\textrm {mm} \times 150$ - $\mu \text{m}$ Si die were acquired in 50 s, and individual line scans in times as short as 500 ms.

High-aspect-ratio (HAR) Ru power rails, buried in front-end-of-line (FEOL) oxide, can potentially replace conventional middle-end-of-line (MOL) Cu power rails. The HAR feature can boost performance by reducing resistance and voltage drop along the power line. The buried nature, helps to minimize standard cell height by freeing up routing resources at MOL, enabling overall area scaling. This paper demonstrates, Ru lines of aspect ratio up to 7, at a CD of 18 nm. Line resistance at these dimensions, measures at 60 Ω/µm, with the minimum electrical resistivity of 8.8 µΩcm, as extracted from the temperature-controlled-resistance (TCR) measurements. HAR Ru lines are also found to withstand very high FEOL thermal budgets, such as 1000 °C activation anneal for 1.5 s. The combination of all these factors, make HAR Ru buried power rail, a promising scaling booster for next generation technology nodes.

We show the first electromigration (EM) failures of full ruthenium interconnects with a cross sectional area of 60nm2. The void is observed at the anode, which demonstrates that in p-type metals, such as Ru, the electromigration force acts in the direction of the electric field. The conventional representation of electromigration as electrons transferring their momentum onto the metal ions, thus has to be adapted for such metals. Moreover, we find that diffusion at the Ru-SiO 2 interface is the dominant diffusion mechanism for EM failure in these specific Ru lines.

This paper reports on the mechanical design, the fabrication technology and the key performance and reliability aspects of novel 0-level thin film vacuum packages for (RF-)MEMS. The packages typically feature a dielectric cap composed of nanoporous alumina and PECVD silicon nitride with a total thickness between 6 and 8.3 μm. The surface micromachining fabrication process is based on a relatively simple method for the wafer-level formation of freestanding nanoporous alumina membranes, featuring extremely narrow cylindrical nanopores with diameters in the range of 10–20 nm and aspect ratio exceeding 100. The package impact on an encapsulated coplanar waveguide (CPW) is minimized (up to 67 GHz) by locally narrowing the RF feedthroughs underneath the package anchor. Furthermore, the hermeticity of various package configurations is evaluated by means of optical monitoring of the cap deflection under different environmental conditions, including short-term exposure to helium and long-term (up to 14 months) exposure to air. Finally, a comprehensive investigation of the reliability of the thin film packages and their compatibility with high-pressure epoxy overmolding 1-level packaging is discussed.

We demonstrate 10 nm half-pitch (HP) Ruthenium interconnects filled by atomic layer deposition (ALD). The resistivity and the cross-sectional area of Ruthenium interconnects were determined via the Matthiessen's rule method. We find that the resistivity of Ru was rather independent of the cross-sectional area of the interconnect, increasing from 12 µΩcm for larger lines to 15–17 µΩcm for cross-sectional areas of 200–300 nm2. 10 nm HP Ru lines showed no electromigration failures at 5 MA/cm2 and 300°C during 1000 hours. Time-dependent dielectric breakdown measurements indicated that Ruthenium does not require a diffusion barrier on both dense and porous low-κ dielectrics.

Cu pumping is the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures during back-end of line (BEOL) processing. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread. As potential BEOL reliability issues due to Cu pumping will first occur at the highest pumping TSVs, they can be mitigated if the fundamental cause for this large intrinsic spread is known and under control. This paper describes a clear correlation between Cu pumping and TSV Cu microstructure based on the grain size at the top of 5×50 μm TSV, disregarding twin boundaries. For the mitigation of TSV Cu pumping the ideal microstructure was shown to consist of a single grain spanning the whole TSV cross section, bringing down the highest measured Cu pumping value from 248 nm to 73 nm. This effect was attributed to the absence of rapid diffusion paths and grain boundary sliding ability.

Irreversible extrusion of Cu from through-silicon vias (TSVs) during high-temperature processing steps presents an important potential back-end-of-line (BEOL) reliability issue. Commonly this reliability risk is mitigated by introducing an anneal after Cu plating for TSV fill. This paper presents the impact of the post-plating anneal temperature and time on residual Cu pumping during a sinter for 20 min at 420 °C, for two different TSV dimensions. Using optical profilometry, in total ~ 4000 TSVs were measured, allowing detailed statistical analysis. Within one sample the Cu pumping values were found to be log normally distributed, implying an intrinsically large spread. Lower residual Cu pumping values were found in TSVs annealed at higher temperatures and for longer times, with the sinter conditions of 20 min at 420 °C confirmed as optimal post-plating anneal conditions. The larger TSVs showed more pumping in the average TSV, but at the tail of the distribution the Cu pumping behavior was the same as for the smaller TSVs. This implies that the impact of Cu pumping on BEOL reliability is identical for both sets of TSV dimensions, suggesting that the impact of Cu pumping on BEOL reliability is not necessarily reduced by reducing TSV dimensions.

A poly-SiGe technology enabling a dense array of micro-cantilevers and tips on CMOS is demonstrated. Built from a dual-thickness structural layer, the cantilevers feature a very small initial bending and have a compliant torsional suspension with a stiffness of 3×10−10 Nm/rad. Sharp tips are formed in a low-temperature amorphous silicon layer by isotropic plasma etching. An electrical read/write system is formed by connecting the tip to the CMOS with a suspended platinum trace, running on top of the cantilever.

In this paper we report for the first time on the fabrication of very reliable CMOS-integrated 10 cm2 11 MPixel SiGe-based micro-mirror arrays on top of 6 level metal CMOS wafers. The array, which is to be used as Spatial Light Modulator (SLM) for optical maskless lithography [1,2,3] consists of 8 mum x 8 mum pixels which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. The pixel density is almost double compared to the state-of-the-art [4]. A stable average cupping below 7 nm, an RMS roughness below 1 nm and long lifetime (>1012 cycles, no creep [5]) are demonstrated.