Search

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.

The temperature dependent carrier transport characteristics of n-type gate-all-around nanowire field effect transistors (GAA NW-FET) on bulk silicon are experimentally compared to bulk fin field effect transistors (FinFET) over a wide range of temperatures (25&ndash, 125 &deg, C). A similar temperature dependence of threshold voltage (VTH) and subthreshold swing (SS) is observed for both devices. However, effective mobility (&mu, eff) shows significant differences of temperature dependence between GAA NW-FET and FinFET at a high gate effective field. At weak Ninv (= 5 &times, 1012 cm2/V∙s), both GAA NW-FET and FinFET are mainly limited by phonon scattering in &mu, eff. On the other hand, at strong Ninv (= 1.5 &times, 1013 cm2/V∙s), GAA NW-FET shows 10 times higher d&mu, eff/dT and 1.6 times smaller mobility degradation coefficient (&alpha, ) than FinFET. GAA NW-FET is less limited by surface roughness scattering, but FinFET is relatively more limited by surface roughness scattering in carrier transport.

New process options in CMOS technology scaling often result in degradation of ESD device performance. TCAD simulations bring an in-depth look at the impact of S/D epitaxy process options with channel strain engineering on CDM-time domain turn-on transient overshoot of ESD diodes in next generation bulk FinFET and GAA technologies.

Beyond dimensional scaling, new process options in CMOS roadmap often result in degradation of ESD device performance. Using 3D TCAD and ESD characterization, the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options are explored on ESD diode performance in next generation bulk FF and GAA technologies.

This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs/n-Si, and n-InAs/n-Ge; and that 2) a TiSi x /12nm Si:P/n-Ge contact with favorable band alignment between Si:P/n-Ge approaches low effective contact resistivity of 1.4×10−8 Ω cm2, close to a record-low value for n-Ge contacts.

The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (VG ~ VD/2). At higher VG closer to VD, cold and hot carrier injection to the oxide bulk defect increases and dominates at the VG=VD stress condition. On the other hand, in short channel devices, hot carriers are generated continuously with respect to VG and highly at VG=VD, and this hot carrier injection into the oxide bulk defect is the main degradation mechanism.

The crystalline orientation effect is investigated for post-treatments of a replacement metal gate (RMG) p-type bulk fin field effect transistor (FinFET). After post-deposition annealing (PDA) and SF6 plasma treatment, the hole mobility is improved. From low-frequency noise analysis, reduction of the trap density and noise level is observed in PDA- and SF6-plasma-treated devices. (100) sidewall-oriented FinFETs show a lower noise level because of fewer interface traps compared to (110) sidewall-oriented devices. SF6 plasma affects the interface traps, whereas PDA relatively more affects bulk oxide traps for RMG high-k last FinFET.

We demonstrate the effectiveness and limitations of critical performance elements in silicon channel bulk finFET CMOS devices featuring embedded Source/Drain (e_SD) dual epi. Further scaling of the fin width below 10nm is shown to impact both the access resistance and S/D overlap capacitances while the mobility behavior for both nMOS and pMOS devices further degrades. Epitaxial S/D regrowth options are optimized to demonstrate ring-oscillator functionality for fin width down to ∼4nm.

© 2015 IEEE. Record-low contact resistivity (pc) for n-Si, down to 1.5×10-9 Q-cm2, is achieved on Si:P epitaxial layer. We confirm that Ti silicidation reduces the pc for n-Si, while an additional Ge pre-amorphization implantation (PAI) before Ti silicidation further extends the pc reduction. In situ doped Si:P with P concentration of 2×1021 cm-3 is used as the substrate, and dynamic surface anneal (DSA) boosts P activation. In addition, TiOx based metal-insulator-semiconductor (MIS) contact is also studied on Si:P but is found to suffer from low thermal stability. ispartof: pages:592-595 ispartof: IEEE International Electron Devices Meeting - IEDM vol:2016-February pages:592-595 ispartof: IEEE International Electron Devices Meeting - IEDM location:Washington, D.C. USA date:7 Dec - 9 Dec 2015 status: published

This paper presents a mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices. Using temperature dependent analysis of effective mobility, quantitative information about the influence of the roughness could be obtained directly on the device. The sidewall and top surface drain current components were estimated from the total drain currents of different fin width conditions. Using a conventional mobility model, it was possible to fit the gate voltage and temperature dependence of sidewall and top surface mobilities. This procedure allowed the contribution of the surface roughness scattering to be quantified with nondestructive characterization. Significant differences were observed for sidewalls and top surface. In the specific case under study, surface roughness scattering on sidewalls was about three times stronger than on top surface for n-channel FinFETs, whereas it remained similar for p-channel ones.

We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved I ON , +15% with Room Temperature (RT) ion implantation (I/I) and +9% with hot I/I, keeping matched Short Channel Effects (SCE) for gate length (L G ) of 30nm compared with As implanted FinFETs. Based on TCAD work, P increases activated dopant concentration in extension compared with As and 5nm fin suppresses off state leakage current under the gate efficiently even in P extension case though P diffusion is faster than As.

A study of the implementation of Ni fully silicided (FUSI) gates to scaled devices is presented, addressing the issue of phase control at short gate lengths. A linewidth effect for Ni FUSI gates is found for non-optimized processes targeting NiSi, with formation of NiSi at long gate lengths and Ni-rich silicides at short gate lengths. This is attributed to Ni diffusion from areas surrounding the gates, resulting in a larger reacted Ni-Si ratio at short gate lengths. The linewidth dependence of the Ni FUSI phase results in an undesirable kink in the V"t roll-off characteristics, due to the difference in effective work function between the Ni silicide phases, which is particularly large for HfSiON dielectrics. An optimized 2-step RTP silicidation process is shown to eliminate this problem allowing the formation of NiSi gates uniformly at all gate lengths. The application and scalability of Ni-rich silicides to PMOS devices is also demonstrated, as well as a scheme for CMOS integration of dual WF phase controlled FUSI (NiSi for NMOS and Ni-rich silicides for PMOS), using an etch back step to reduce the poly-Si height on PMOS electrodes before full silicidation.

Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45° rotated devices compared with the 0° rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45° rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv-exhibited when transitioning from planar to FinFET architecture at 45° rotation-plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45° rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho et al.

Post-treatment of replacement metal gate is investigated for the device performance improvement of high- k last p-type bulk FinFET using post-deposition annealing (PDA) and SF6 plasma treatment. Compared with untreated HfO2 reference, post-high- k deposition PDA and SF6 plasma-treated devices show improved driving current and hole mobility. With the carrier number fluctuations with correlated mobility fluctuation model, ~3 times lower input gate referred noise is observed in PDA and SF6 plasma-treated devices compared with untreated FinFETs. Post-treatments suppress the trap density of high- k last FinFET. PDA reduces oxide bulk trap whereas SF6 plasma affects both interface and oxide bulk trap.

A study of the negative and positive bias temperature instability (N/PBTI) reliability of FinFETs with different TiN metal gates deposited by either atomic layer deposition (ALD) or physical vapor deposition (PVD) on HfO2 dielectrics found that the nonuniformity of the interfacial oxide layer is closely related to reliability characteristics. FinFETs with an ALD TiN gate exhibit better NBTI and PBTI lifetimes than those with a PVD TiN gate. In addition, the dependence of fin width on NBTI reliability appeared to be worse with narrower fins, whereas PBTI reliability improves.

Superior reliability of junctionless (JL) compared with inversion-mode field-effect transistors (FETs) is experimentally demonstrated on bulk FinFET wafers. The reduced negative bias temperature instability (NBTI) of JL pFETs outperforms the previously reported best NBTI reliability data obtained with Si channel devices and guarantees 10-year lifetime at typical operating voltages and high temperature. This behavior is understood through the reduced oxide electric field and lessened interaction between charge carriers and oxide traps during device operation. These findings encourage the investigation of JL devices with alternative channels as a promising alternative for 7-nm technology nodes meeting reliability targets.

This work provides for the first time an experimental assessment of the impact of thermo-mechanically induced stresses by copper through-silicon vias, TSVs, on fully depleted Bulk FinFET devices. Both n and p type FinFETs are significantly affected by TSV proximity, exhibiting lower impact on drive current with respect to the planar devices. The obtained results are in agreement with the thermo-mechanical models for Cu-TSV and are supported by the 4 point bending stress calibration.

NBTI characteristics of p-FinFET with TiN metal gates deposited by ALD or PVD method have been investigated in detail. NBTI lifetime of ALD-TiN gate device was better than that of PVD TiN gate device. The differences were primarily attributed to the differences in the thickness and quality of interfacial SiO 2 layer which was affected by an oxygen scavenging reaction of TiN layer. Also, NBTI characteristics were degraded at narrower FinFET in both ALD and PVD devices as the contribution from sidewall (110) region increased.

We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show smallest time-dependent variability. Furthermore, we report comprehensive measurements of the impact of individual trapped charges on the entire FET ID-VG characteristic. Comparing with 3D atomistic device simulations, we identify several characteristic behaviors depending on the interplay between the location of the oxide defect and the underlying random dopant distribution.

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.

A novel bulk-Si based pMOSFET structure is presented featuring a high-mobility SiGe 0.45 channel and raised SiGe 0.25 source/drains. This device offers enhanced scalability with respect to standard pMOS devices, leading to 50% improved drive current. 30nm gate length devices show a high drive current of ∼580 µA/µm for I OFF =100nA/µm, DIBL=126mV/V, SS=80mV/dec, showing superior electro- statics without halo implants. Finally, the compatibility with additional strain-boosters is demonstrated.

This work demonstrates the successful integration of 0.85nm-EOT Si 0.45 Ge 0.55 -pFETs using a gate first approach. An in-depth analysis, ranging from capacitor-level up to circuit-level is carried out, with systematic benchmarking to a conventional Si-channel reference. Outperforming the state-of-the-art Si 0.55 Ge 0.45 -pFETs, an I ON of 630µA/µm at L G_POLY = 35nm with I OFF = 100nA/µm and V DD = −1V has been achieved without any epi-S/D boosters. Significant improvements at lower V DD have also been confirmed through complex circuit simulations and validated by experimental results.

We report low V t (V t,Lg=1µm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ∼8A using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3A reduction in nMOS and pMOS T inv (2) 220mV lower long channel pMOS V t (3) 21%/12% pMOS/nMOS drive current increase at I off =100nA/µm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T inv of 12A, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.

Carbon-based thermal stabilization techniques have been used for improving performance of CMOS periphery devices in memory application. Current drives are shown to improve by 15 and 30% for N & PMOS, respectively, external resistance of P+ improves by 15 X and N+ by 30%, and RO delay reduction of 25% compared to the conventional contact scheme.

The Ni-silicide phase formation in FUSI gates was investigated comparing soak and spike anneals for the first RTP step. From both physical analysis on blanket wafers and electrical measurements on nMOS FUSI/HfSiON device it is found that the RTP1 temperature process window (PW) to obtain NiSi or Ni3Si2 at the FUSI/dielectric interface is significantly widened for spike anneals (30degC < PW < 50degC) compared to soak anneals (15degC < PW < 25degC). Good overlap between the RTP1 process window for nMOS (NiSi or Ni3Si2 at the FUSI/dielectric interface) and the RTP1 process window for pMOS (Ni-rich silicide at the interface) is achieved by the reduction of the poly-Si height for the pMOS gate.

In this paper, authors investigated for the first time the effective mobility (?eff) in short-channel FinFET transistors. Dedicated test structures for Radio-Frequency (RF) split C-V measurements enabled short-channel FinFET C-V measurements, and consequently, accurate effective channel length (Leff) calculation for reliable ?eff extraction. ?eff is extracted for FinFETs down to dimensions of 60nm fin height, 25nm fin width and 70nm Leff, with Poly-Si/MOCVD-TiN gate stacks on SiON dielectrics. Promising non-degraded Long/Short channel hole mobility behavior is reported, whereas electron mobility decreases with Leff.

This work presents the use of ultimately thin (15 nm) L-shaped spacers to open the process window for deposition-related steps. Whereas conventional spacers prevent the correct active area silicidation between two closely located transistors, these thin L-shaped spacers allow the formation of a low resistive active interconnect between transistors as close as 40 nm apart. With respect to conventional spacers, thin L-shaped spacers show equally good silicide bridging immunity, device characteristics and electrostatic discharge performance.