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Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

This work presents experimental evidence of the formation mechanisms of few-layer graphene (FLG) films on SiC by nickel silicidation. FLG is formed by annealing of a 40 nm thick Ni layer on 6H-SiC at 1035ºC for 60 s, resulting in a Ni2Si layer which may be capped by any Ni that did not react during annealing. It has been proposed that FLG forms on top of the Ni during the high temperature stage. In contrast, during cooling, carbon atoms which were released during the silicidation reaction may diffuse back towards the Ni2Si/SiC interface to form a second FLG film. After annealing, layer-by-layer de-processing was carried out in order to unequivocally identify the FLG at each location using Atomic force microscopy (AFM) and Raman spectroscopy.

For the first time, we have established a replacement metal gate complementary metal-oxide-semiconductor process flow for the high temperature ion implantation of bulk Si fin field-effect-transistors on a 45-nm fin pitch design rule, using high temperature spin-on-carbon hard mask and a dedicated patterning process. In this paper, the advantages of high temperature ion implantation and a detailed process flow of the dedicated patterning are explained. Electrical characteristics of metal-oxide-semiconductor field-effect-transistors and ring oscillators are evaluated.

We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.

First results obtained from electron beam annealed sequentially implanted Pb+ (29 keV) and Se+ (25 keV) ions into a SiO2 matrix are presented. Key results from Rutherford backscattering spectrometry and transmission electron microscopy investigations are: (1) Pb and Se atoms are found to bond in the SiO2 matrix during implantation, forming into nanoclusters even prior to the annealing step, (2) Pb and Se atoms are both present in the sample after annealing at high temperature (T = 760 °C, t = 45 min) and form into PbSe nanoclusters of varying sizes within the implanted region, and (3) the broader concentration profile of implanted Se creates a number of secondary features throughout the SiO2 film, including voids and hollow shell Se nanoclusters. A sequential ion implantation approach has several advantages: selected areas of nanocrystals can be formed for integrated circuits, the technique is compatible with present silicon processing technology, and the nanocrystals are embedded in an inert matrix – making them highly durable. In addition, a higher concentration of nanocrystals is possible than with conventional glass melt techniques.

The formation and subsequent time-evolution of silicon carbide nanocrystals grown on a silicon surface by high-temperature vacuum annealing was investigated, with the effects of carbon contamination on the properties of these nanostructures being examined. The presence of higher contaminant levels during an annealing step was found to strongly enhance the nanocrystal growth rate, yet conversely to have no effect upon the density of nanocrystals which nucleated on the silicon surface. The physical structure of these objects was then studied in detail using high-resolution imaging and surface analysis techniques.

Strongly-enhanced desorption of a thick (100 nm) silicon oxide layer by the pre-sputtering of a thin germanium surface film was observed under high-temperature vacuum annealing conditions. High-resolution SEM imaging reveals that germanium nanoislands are first formed on the sample surface, and that these then act as nucleation centres for the formation of voids in the oxide, leading to a rapid desorption of the silicon oxide layer. EDS analysis of the silicon surface after oxide decomposition shows that the introduced germanium impurities are fully consumed in this desorption process.

A unique detection system has been developed which allows for the counted implantation of individual low-energy heavy ions into silicon. This system can ensure the placement of individual ions at precise locations within a wafer using an EBL-machined resist mask, and utilizes the generation of ionization within the silicon substrate to allow for the reliable detection of implants down to 14 keV. Due to the necessity for low-noise operation, it is important that both the capacitance of the detectors and their leakage current be reduced as much as possible. To this end, we have now created a detector architecture with a measured capacitance of 0.6 pF and sub-pA leakage current at liquid nitrogen temperature, which has allowed us to achieve a resolution of 410 eV (44.2 electrons RMS) when coupled to low-noise signal-processing electronics and operated at 90 K.

We demonstrate time-resolved control and detection of single-electron transfers in a silicon device implanted with exactly two phosphorus donors. Charge state relaxation at millikelvin temperature is shown to be dominated by phonon emission and background charge fluctuations for low energies, while higher-order processes take over at higher energies. Our results reveal relaxation times for single-donor charge states of several milliseconds, which have significant implications for single-atom nanoelectronics.

In the near future devices which are fabricated from shallow arrays of few and single atoms will exploit quantum mechanical rules to perform useful functions including quantum computation. Fabrication of these devices presents formidable technological challenges. We have developed a single ion implantation system that is capable of verifiable fabrication of single donor devices using 14 keV 31 P ions implanted into ultra-pure, high resistivity silicon substrates based on the technique of Ion Beam Induced Charge (IBIC). A detection system with integrated detector electrodes registers the charge transient from a single ion impact which is used to signal the implantation of an ion into the substrate. We describe here the use of IBIC with MeV ions to study the charge collection efficiency of the detector electrodes. By using three dimensional numerical technology computer-aided design (TCAD) models for the decrease in the IBIC signal as a function of distance from the detector electrode, we can obtain an accurate measurement of the resistivity of the silicon substrate, allowing confirmation of the values specified by the supplier, and providing us with confidence in the numerical models used by TCAD for simulation. This technique has advantages over resistivity measurements by four-point probes because it is spatially resolved, probes through the intact oxide, and can be done without making contact to the device in the area of the probe.

We have developed a novel technique based on the selective desorption of an oxide film in order to grow ordered arrays of silicon carbide nanocrystals on a silicon surface. These nanocrystals form as a byproduct of void nucleation in the oxide during the high-temperature vacuum annealing of silicon, a process which normally produces a random distribution of nanocrystals across the silicon surface after its oxide layer has been fully desorbed. By the pre-deposition of a thin layer of excess silicon on the oxide surface through a patterned lithography mask, site-specific nucleation of voids in the silicon oxide can instead be achieved during the annealing step, leading to the growth of silicon carbide nanocrystals in regular patterns over the silicon surface.

We review an ongoing effort to demonstrate technologies required for quantum computing with phosphorus donors in silicon. The main aspect of our research is to achieve control over charge and spin states of individual dopant atoms. This work has required the development of new techniques for engineering silicon nanodevices at the atomic level. We follow an approach for implanting single phosphorus ions into silicon substrates with integrated p–i–n detectors. Configuring our devices with radio-frequency single-electron transistors (RF-SETs) allows for charge sensing at low temperatures. In this context, we perform measurements of single-electron charge transfer between individual phosphorus donors. In a parallel effort, we employ nanoscale Schottky contacts for populating and depopulating individual dopant atoms. Of particular interest is coherent manipulation of single-electron charge and spin states on individual dopant atoms. Charge manipulation between coupled donor states may be achieved by either external microwave pumping or intrinsic tunnel coupling. Spin manipulation, on the other hand, involves magnetic resonance. In this context, we pursue electrically detected spin resonance in phosphorus-doped devices with a decreasing number of dopant atoms.

A method of single ion implantation based on the online detection of individual ion impacts on a pure silicon substrate has been implemented in a focused ion beam (FIB) system. The optimized silicon detector integrated with a state-of-art low noise electronic system and operated at a low temperature makes it possible to achieve single ion detection with a minimum energy detection limit about 1 to 3.5 keV in a FIB chamber. The method of single ion implantation is compatible with a nanofabrication process. The lateral positioning of the implantation sites are controlled to nanometer accuracy (~5 nm) using nanofabricated PMMA masks. The implantation depth is controlled by tuning the single ion energy to a certain energy level (5-30 keV). The system has been successfully tested in the detection of 30 keV Si+ single ions. The counting of single ion implantation in each site is achieved by the detection of e-h pairs (an outcome of ionization energy) produced by the ion-solid interaction; each 30 keV Si+ ion implanting through a 5 nm SiO2 surface layer and stopping at a pure silicon substrate produces an average ionization energy about 7.0 keV. A further development for improving a detection limit down to less than 1 keV in FIB for low energy phosphorus implantation and detection is outlined. Fabrication of nanometer-scaled phosphorus arrays for the application of qubits construction is discussed.

We report recent progress in single keV ion implantation and online detection for the controlled implantation of single donors in silicon. When integrated with silicon nanofabrication technology this forms the “top down” strategy for the construction of prototype solid state quantum computer devices based on phosphorus donors in silicon. We have developed a method of single ion implantation and online registration that employs detector electrodes adjacent to the area into which the donors are to be implanted. The implantation sites are positioned with nanometer accuracy using an electron beam lithography patterned PMMA mask. Control of the implantation depth of 20 nm is achieved by tuning the phosphorus ion energy to 14 keV. The counting of single ion implantation in each site is achieved by the detection of e-/h+ pairs produced by the implanted phosphorus ion in the substrate. The system is calibrated by use of Mn K-line x-rays (5.9 and 6.4 keV) and we find the ionization energy of the 14 keV phosphorus ions in silicon to be about 3.5-4.0 keV for implants through a 5 nm SiO2 surface layer. This paper describes the development of an improved PIN detector structure that provides more reliable performance of the earlier MOS structure. With the new structure, the energy noise threshold has been minimized to 1 keV or less. Unambiguous detection/counting of single keV ion implantation events were achieved with a confidence level greater than 98% with a reliable and reproducible fabrication process.

Studies of electrical transients in single-crystal silicon induced by discrete low-energy (sub-20 keV) ions have been carried out at 90 K, with ionization measurements and damage accumulation in the sample being investigated. Ionization studies reveal a discrepancy between experimental results and predictions from the widely used SRIM (stopping and range of ions in matter) code, one which increases with decreasing energy: a result which has previously been suggested from studies with continuous ion beams. Damage accumulation studies of the sample also demonstrate that current models of damage build-up in silicon are inadequate at such low energies, with experiments indicating that individual ions create a much larger region of decreased charge collection efficiency outside of the small amorphous cores known to be formed by such impacts.

We demonstrate a method for the controlled implantation of single ions into a silicon substrate with energy of sub-20‐keV. The method is based on the collection of electron-hole pairs generated in the substrate by the impact of a single ion. We have used the method to implant single 14‐keV P31 ions through nanoscale masks into silicon as a route to the fabrication of devices based on single donors in silicon.

The authors have developed a technique which enables the implantation and detection of single low-energy (