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This paper presents a design methodology for robust and low-energy clock networks for ultralow voltage (ULV) circuits. We show that both clock slew and skew play important roles in achieving high maximum operating frequency (F\max) and low clock energy in ULV circuits. In addition, clock networks in ULV circuits are highly sensitive to process variations. We propose a variation-aware methodology that controls both clock skew and slew to maximize F\max and minimize clock power. In addition, we implement dynamic programming (DP)-based ULV clock routing and buffering methods (deferred merging and embedding) for deterministic and statistical conditions. Experimental results show that our clock network design method achieves lower energy (more than 20% savings) at comparable or even higher F\max compared with the existing methods. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the variability in a 3-D clock network designed with single and multiple through-silicon vias and present a post-silicon tuning methodology, called tier adaptive body biasing (TABB), to reduce skew and data path variability in 3-D clock trees. TABB uses specialized on-die sensors to independently detect the process corners of n-channel metal–oxide–semiconductor (nMOS) and p-channel metal–oxide–semiconductor (pMOS) devices and accordingly tune the body biases of nMOS/pMOS devices to reduce the clock skew variability. We also present the system architecture of TABB and circuit techniques for the on-die sensors. Circuit-level simulation and statistical analysis of the TABB architecture in a predictive 45-nm technology demonstrate the effectiveness of TABB in reducing the clock skew variability considering the data path variability in 3-D ICs. [ABSTRACT FROM AUTHOR]

This paper presents the effect of proactive spatiotemporal power multiplexing on the thermal field in many-core processors. Power multiplexing migrates the locations of active cores within a chip after each fixed time interval, referred to as the migration interval, to redistribute the generated heat and thereby reduce the peak temperature and spatial and temporal nonuniformity in the thermal field. Clock and supply gating is used to minimize the power of the deactivated cores. The control of the migration interval is studied considering a 256-core processor at the predictive 16-nm node to evaluate the conflicting impact of the migration interval on thermal field and system performance. [ABSTRACT FROM PUBLISHER]

In this paper, we analyze the effect of clock slew in subthreshold circuits. Specifically, we address the issue that variations in clock slew at the register control can cause serious timing violations. We show that clock slew variations can cause frequency targets to deviate by as much as 28% from the design goals. Based on these observations, we recognize the importance of clock slew control in subthreshold circuits. We propose a systematic approach to design the clock tree for subthreshold circuits to reduce the clock slew variations while minimizing the energy dissipation in the tree. The combined approach, including the wire sizing and dynamic nodal capacitance control, can achieve better slew control (and better timing control) at lower energy in subthreshold circuits. [ABSTRACT FROM PUBLISHER]