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This paper discusses the design of a driver amplifier operating in the Ku-band using a 130 nm SOI CMOS process. The amplifier consists of two stages: a cascode amplifier in the first stage for high gain, and a CS amplifier in the final stage for high OP1dB. In the cascode amplifier structure of the first stage, a series inductor is added between the CS and CG amplifiers to simplify input matching. This modification shifts the maximum Gm point of the cascode amplifier to a lower frequency, resulting in a high gain at the target frequency. The measured amplifier achieves a maximum gain of 13.7 dB and an OP1dB of −0.3 dBm. It consumes 12 mW of power at 1.2 V and occupies an area of 0.188 mm², excluding the DC and RF pads. [ABSTRACT FROM AUTHOR]

In the front-end receiver of a GPS, the noise figure is extremely important and requires a low-noise amplifier with a low noise figure and small size. This study aims to investigate the design of an L-band low-noise amplifier using the 0.18-μm CMOS process. For low-noise characteristics, the input series inductor was removed, the effective width of the transistor was increased to achieve impedance matching, and the inductors requiring high inductance had laminated structures with small chip sizes. The low-noise amplifier achieved a noise figure of less than 2.5 dB, a return loss of more than 10.57 dB, a peak gain of 17.3 dB, and a size of 1.05 mm×0.78 mm in frequency from 1.4∼2.1 GHz. [ABSTRACT FROM AUTHOR]

This paper presents the design of a driving amplifier intended for use in W-band RFICs. The amplifier adopts a differential two-stage common-source configuration to ensure robust output power. Furthermore, it has been enhanced through the incorporation of a neutralized capacitor to improve stability and maximize gain. The driving amplifier was fabricated using a 65-nm bulk CMOS process for validation. The measured performance of the amplifier demonstrated characteristics, including an input/output return loss exceeding 10 dB and a peak gain of 14.1 dB, achieved within the frequency range of 77∼88 GHz. The power consumption of the amplifier was only 34 mW at a voltage of 1 V, and it exhibited an OP1dB of 3.8 dBm. The size of the driving amplifier, excluding DC and RF pads, was 0.401×0.14 mm². [ABSTRACT FROM AUTHOR]

This paper presents the design of W-band Wilkinson power divider using 65 nm bulk CMOS process. In this design, the quarter-wavelength (λ/4) transmission line was replaced with a lumped element, and a CRC structure was applied to the isolation network circuit. In addition, a metal wall was installed between the two output lines to enhance isolation. This power divider had a maximum insertion loss of 1.93 dB and a minimum isolation of 13.3 dB in the 75~110 GHz band. The return loss was more than 7.2 dB, and the size of the core was 0.2×0.12 mm². [ABSTRACT FROM AUTHOR]

This study presents a Q-band wideband low-noise amplifier (LNA), which is implemented and verified using a 65-nm bulk CMOS process, for millimeter-wave applications. The proposed low-noise amplifier uses a transformer structure at the input stage to obtain broadband input-matching characteristics. Under 1-V supply voltage, the proto-type LNA achieves a simulated peak gain of 22.74 dB with gain variation of ±0.37 dB in frequency band. The simulated noise figure (NF) was 3.27 dB at 40 GHz while consuming 17 mW. The core occupies an area of 0.13 mm². [ABSTRACT FROM AUTHOR]