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CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

A channel-selecting low-noise amplifier (CS-LNA) with blocker filtering is presented for a SAW-less diversity path receiver (RX) in frequency-division duplexing cellular systems. A hybrid N-path bandpass filter/band-reject filter (BPF/BRF) feedback network is applied to the LNA to create close-in reject bands around the passband to suppress transmit leakage and improve the out-of-band (OOB) input-referred third-order intercept point (IIP3). Control of the frequency and depth of the reject bands is demonstrated with analysis and simulation. A gm2{\mathchar"702D}gm3 cancellation linearization is applied to improve the in-band (IB) linearity. Adaptive LO swing and silicon-on-insulator (SOI) thick-oxide devices are demonstrated to improve the power-handling capability. The proposed CS-LNA is implemented in 32-nm CMOS SOI and operates from 0.4 to 6 GHz with the maximum rejection larger than 60 dB and power-handling capability up to 17 dBm. The prototype demonstrates an OOB IIP3 of 36 dBm and IB IIP3 of 10 dBm at 1 GHz. To the authors’ knowledge, this is the highest blocker rejection, power-handling capability, linearity, and the widest tuning range for an LNA with tunable filtering. [ABSTRACT FROM PUBLISHER]

A tunable N-path filter with more than one decade tuning range is demonstrated to address transmit (TX) leakage in a surface-acoustic-wave-less diversity path receiver for frequency-division duplexing cellular systems. The proposed filter simultaneously creates a reject band and passband anywhere from 0.2 to 3.6 GHz to suppress TX leakage while minimizing insertion loss of the receive signal and is implemented in 45-nm CMOS silicon-on-insulator. Measurements show the 3-dB bandwidth of the passband is greater than 80 MHz with an independently tunable reject band, providing the ultimate rejection is from 33 to 41 dB while the passband insertion loss is between 2.6 dB and 4.3 dB over the tuning range. The proposed filter offers 29-dBm out-of-band (OOB) third-order input-intercept power (IIP3) and 22-dBm in-band (IB) IIP3 with a 10-dBm blocker 1-dB compression point (B1dB). To the authors’ knowledge, this is the highest B1dB, IB IIP3, and OOB IIP3 for a CMOS tunable filter. [ABSTRACT FROM PUBLISHER]

Circulators and quasi-circulators (QCs) have a tradeoff between maximum isolation and bandwidth. We present a tunable distributed active circuit to achieve high isolation over a wide frequency range. The reported QC provides more than 40-dB suppression between transmit (TX) output signal at the antenna and TX leakage into the receive (RX) port over a tuning range of 5.3–7.3 GHz in small-signal operation. Large-signal TX-RX suppression is optimized across power level. The TX output achieves peak power of 18 dBm and 12% power-added efficiency at 6.3 GHz. The QC is designed in a high-resistivity 45-nm CMOS silicon-on-insulator process and occupies an area of 1.62~ \text mm \times 0.97~ \text mm . [ABSTRACT FROM PUBLISHER]

This paper reports the generation, amplification, and radiation of modulated signals at 45 GHz using a single-chip CMOS power amplifier coupled to a 2\, \times \,2 antenna array. Using digital predistortion, complex constellations were demonstrated for wide modulation bandwidth, which allows high data rates to be transmitted in a spectrally efficient manner. After predistortion, a 98-MS/s 1024-QAM signal with peak-to-average power ratio of 7 dB was demodulated with an error vector magnitude of 1.3%. The measured equivalent isotropically radiated power was 26.2 dBm. The corresponding average RF power produced by the CMOS chip, considering a simulated antenna gain of 12 dB, was 14.2 dBm. [ABSTRACT FROM PUBLISHER]

A 45 GHz active phase-shift Doherty PA is proposed and implemented in 45-nm SOI CMOS. The quarter wave-length transmission line at the input of the auxiliary amplifier is replaced by an amplifier, increasing the gain and PAE by more than 1 dB and 5%, while reducing the die area. Use of slow-wave coplanar waveguides (S-CPW) improves the PAE and gain by approximately 3% and 1 dB, and further reduces the die area. Two-stack FET amplifiers are used as the main and auxiliary amplifiers, allowing a supply voltage of 2.5 V and increasing the output power. The active phase-shift Doherty amplifier demonstrates a peak power gain and PAE of 8 dB and 20% at 45 GHz. It occupies 0.45 mm^2, and at 6-dB back-off power, the PAE is 21%. [ABSTRACT FROM AUTHOR]

Stacked field-effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors. The stacking of multiple FETs allows increasing the supply voltage, which, in turn, allows higher output power and a broader bandwidth output matching network. Different matching techniques for the intermediate nodes are analyzed and used in two-, three-, and four-stack single-stage Q-band CMOS PAs. A four-stack amplifier design achieves a saturated output power greater than 21 dBm while achieving a maximum power-added efficiency (PAE) greater than 20% from 38 to 47 GHz. The effectiveness of an inductive tuning technique is demonstrated in measurement, improving the PAE from 26% to 32% in a two-stack PA design. The input and output matching networks are designed using on-chip shielded coplanar waveguide transmission lines, as well as metal finger capacitors. The amplifiers were implemented in a 45-nm CMOS silicon-on-insulator process. Each of the amplifiers occupies an area of 600 \mum\,\times\,500 \mum including pads. [ABSTRACT FROM AUTHOR]

This paper presents passive integrated circuits for millimeter-wave transmitters and receivers implemented in a 45-nm CMOS silicon-on-insulator (SOI) process. The advantages of SOI over bulk CMOS are discussed for millimeter-wave passive circuits. First, a single pole double throw (SPDT) switch demonstrates a measured insertion loss of less than 1.7 dB at 45 GHz and third-order intermodulation intercept point (IIP3) of 18.2 dBm. Second, a double-balanced passive in-phase/quadrature (I/Q) mixer exhibits a conversion loss of 8.35 dB at 44 GHz and IIP3 of 15.5 dBm. At a fixed IF of 200 MHz, the minimum I/Q gain and phase imbalance is 0.25 dB and 1.9^\circ. The passive mixer and SPDT switch results demonstrate a record minimum insertion loss and linearity performance for the passive millimeter-wave circuits. [ABSTRACT FROM AUTHOR]

This paper presents a pulse-compression radar baseband analog signal processing integrated in a silicon process for low cost and power dissipation. The analog signal-processing circuitry exhibits the autocorrelation properties of the polyphase codes, maximizes the sensitivity and resolution of a pulse radar system, and alleviates speed and resolution requirements of the analog-to-digital converter (ADC) via an analog correlator. The circuitry includes a two-stage variable gain amplifier (VGA) for high dynamic range, a correlator/integrator circuit, a comparator, and offset calibration circuits. The differential 6-bit VGA is designed to adaptively track the Friis path loss through rapid change of the VGA gain and offset calibration, relaxing the dynamic range requirements of the correlator. The measured performance shows a VGA gain variation of 52 dB and a VGA group-delay imbalance of 50 ps over 64 states. The high-speed pulse compression/correlation is performed in analog current domain and the speed requirement on the ADC is reduced by a factor equal to the duty cycle lowering the ADC power consumption. The chip is fabricated in a 90-nm process, wire bonded on the FR4 printed circuit board, and tested with a Stratix IV field-programmable gate-array board to evaluate the system performance for different radar polyphase codes. [ABSTRACT FROM AUTHOR]

A dual-channel CMOS distributed amplifier (DA) is proposed for a highly linear receiver front-end. Proper choice for the number of stages and cutoff frequency of the distributed circuit realizes isolation between amplifier channels. Analysis of the distributed circuit describes the role of reverse gain in minimum noise figure (NF) and intermodulation distortion. The chip is fabricated in a \0.13-\mu\ m CMOS process, occupies an area of \ 0.60 mm^2, and consumes 18 mW from a 1.2-V supply. Measurements of the DA show an NF of 5.7 dB, an output P1~{dB} of 4.9 dBm, and a forward gain of 9.6 dB at 24 GHz. [ABSTRACT FROM AUTHOR]

A fully-differential, 16-path bandpass filter (BPF) is demonstrated with wide tuning range, high linearity for and wideband harmonic rejection. The reconfigurable filter and clock generation circuitry is fabricated in IBM 45 nm CMOS SOI. To cover a tuning range of one decade (250 MHz to 2250 MHz), a 16-path scheme eliminates harmonic aliasing component to 15th harmonic of the local oscillator. The BPF has a 3 dB bandwidth greater than 20 MHz and 0.9 dB insertion loss. The BPF also achieves high linearity with an out-of-band IIP 3 > 27 ~dBm and P1dB > 3 ~dBm. The BPF tolerates blockers to 9 dBm 1 dB desensitization point (B1dB). [ABSTRACT FROM PUBLISHER]

An Si photonic transmitter is integrated in a 130-nm silicon-on-insulator complementary metal–oxide–semiconductor technology. A high-speed photonic ring modulator is designed for 25-Gb/s operation with an 8-dB extinction ratio. The ring is driven with a 2.4\-Vpp swing using a low-power inverter driver. With a reference receiver, the 25-Gb/s link is measured with a bit error rate (BER) of 10^-12. The total transmitter power consumption is 17 mW at 25 Gb/s for an energy efficiency of 680 fJ/b excluding laser and ring tuning power. [ABSTRACT FROM PUBLISHER]