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This article presents a 9-bit 500-MS/s 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with an error-tolerant interpolation technique. The proposed interpolation technique uses flip-flops to implement a 2-bit/cycle operation in the SAR ADC. By taking advantage of the metastable region of the flip-flop, the proposed interpolator can defer the bit decision when a decision error occurs with a high probability. Because the SAR ADC approximates the signal range step by step, the deferred decisions proceed to the next conversion cycles without any increase in quantization noise. The deferring-decision characteristic increases the error tolerance in the presence of comparator mismatches and increases the inherent linearity of the interpolation technique compared to conventional latch interpolation. A prototype ADC was designed using the 28-nm CMOS technology to verify the effectiveness of the proposed interpolation technique. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at the Nyquist rate are 50.6 and 61.4 dB, respectively. The power consumption is 1.87 mW at a sampling frequency of 500 MS/s. The proposed ADC achieves a Walden figure of merit (FoM) of 13.5 fJ/conversion-step.

This paper presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic random-access memory interface in 28-nm CMOS technology. A direct input-output comparison using a sub-sampling technique reduces the effect of a timing mismatch of a replica delay line for synchronizing an input clock and output strobe clock. A divided clock samples the input clock for phase alignment. A 4-b analog-to-digital converter was used for input phase acquisition. The output phase is aligned with respect to the sampling clock phase using a bang-bang phase detector. Two DLLs for the input-output synchronization are implemented in a cascade structure, and the loop delay of the replica delay line is considerably reduced. In the proposed DLL, a PR delay line using an 8-phase clock generator is adopted for linearity to reduce the phase difference of the phase interpolation from π/2 to π/4. The resolution of the PR-DLL is 7-b of 2π, which consists of a 3-b coarse and a 4-b fine control. The DLL operates from 2.4 to 8 GHz, and the power dissipation at the maximum input frequency is 20.2 mW. The measured clock root mean square jitter was 1.68 ps. According to the simulation results, the phase mismatch between the input and output clocks was reduced by 80.5%.

This article presents a 0.975-pJ/bit 56-Gb/s pulse amplitude modulation-4 (PAM-4) receiver using a time-based least significant bit (LSB) decoder in 28-nm CMOS technology. The proposed time-domain decision technique improves the robustness of comparator voltage variations by separating the data and reference paths. If the reference voltage difference is constant regardless of the common-mode voltage shift, the time-domain decoder achieves a low bit error rate (BER). To improve the timing margin of the LSB decoder from the data-dependent jitter, a sample-and-hold (S/H) structure is adopted in both the data and reference paths. The S/H circuits extend the timing margin by converting the input of the comparators to a constant voltage. The number of comparators for data decoding is reduced to two-thirds, and only eight comparators are required for a quarter-rate structure. The number of comparators in the data path, excluding the reference path, is 4, which reduces the loading capacitance. An adaptive threshold voltage calibration was implemented to generate the timing reference pulse. In addition to bathtub graphs, the BER, according to the $ {V_{CM}}$ change of the reference voltages, is plotted to show the sensitivity to the voltage variation.

This brief presents a low-power counter-based adaptive equalizer that does not require additional power-hungry comparators for an equalizer adaptation loop. A pulse generator in the proposed equalizer obviates the need for additional error sampling comparators. Instead, it allows the receiver to utilize an output of a data decision comparator for the equalizer adaptation by generating a pulse that indicates whether the comparator makes a firm decision for the incoming data. A single comparator is shared by the data recovery path and equalizer adaptation loop. Consequently, the proposed counter-based equalizer achieves a low power dissipation owing to the reduced number of comparators. Fabricated in a 28-nm CMOS technology, the prototype receiver occupies an active area of 0.004 mm2 and consumes only 0.99-pJ/b at 15-Gb/s.

This article presents an receiver (RX) only equalization (ROE) technique that eliminates feed-forward equalization (FFE) in transmitter (TX) and bandwidth improved output driver without increment of power consumption. With a help of the proposed design technique, the power consumption, circuit complexity, and design cost are improved. The proposed RX with one-tap finite-impulse response (FIR) and second-tap IIR decision feedback equalizer (DFE) removes the FFE equalization in TX by moving the sampling point of main cursor in the received data. A simpler TX architecture with nMOS only output driver (NOD) owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) operation. The proposed transceiver was fabricated in a 65-nm CMOS technology. The RX achieves bit error rate (BER) less than $10^{-12}$ over a 22-dB channel loss at 32 Gb/s with 0.62-pJ/bit energy efficiency, and the TX with NOD has 0.77- and 0.40-pJ/bit energy efficiency at 32 Gb/s in differential mode and single-ended mode, respectively. The occupied area of TX and RX is 0.002 and 0.024 mm2, respectively.

This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output clock of a digitally controlled oscillator (DCO) for both the equalizer adaptation and clock recovery loop, the proposed adaptive equalizer is combined with the CDR by sharing its adaptation loop including a sub-sampling phase detector (SSPD) and a digital logic circuit. Consequently, the active area and power dissipation for the adaptive equalizer are reduced. Furthermore, the SEC is proposed to improve the high-frequency jitter tolerance of the CDR. The SEC detects bit errors by observing the comparator decision and corrects the errors without any data encoding or complicate circuits. The out-of-band jitter tolerance is improved by 22.6% at 100 MHz for 17.2-dB loss channel with −12 bit-error rate (BER) with the proposed SEC. The SEC is applicable to various receivers with compact design at a low cost. The prototype receiver consumes 23.9 mW at 14-Gb/s and occupies 0.007 mm2 in a 28-nm CMOS technology.

In an effort to keep pace with bandwidth growth, DRAM employes the quad data rate (QDR) to transfer four data in one clock cycle. In recent graphic memories, QDR is being implemented by a phase-locked loop (PLL). However, it is hard to apply a PLL to main and mobile memories for its high power dissipation and hardware cost. Therefore, we propose a new delay-locked loop-based quadrature clock generator (DLL-QCG) to replace a PLL. A sub-range technique is adopted for a phase interpolator (PI) to achieve a very fine resolution with low power and small area. A tiny resolution mitigates the jitter accumulation effect of the conventional all-digital DLL-QCG and reduces a phase error. With the introduction of the sub-range PI, the delay line structure is changed from two-stage (coarse-fine) to three-stage (coarse-fine-finer). To control this, we also develop a new controller, which ensures clock quality through seamless boundary switching at the fine-to-finer. The circuit is fabricated using a 28 nm CMOS FDSOI technology with a 1 V supply voltage and an area of 0.0072 mm2. It operates from 1.8 to 2.5 GHz and achieves a phase error of 3.35° to 6.35° without a quadrature-phase collector. In addition, the measured RMS and peak-to-peak jitters at operating bandwidth are 1.05 to 1.71 ps and 8.4 to 12 ps, respectively.

This brief presents a 10-bit ultra-low power energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). A new adaptive-reset switching scheme is proposed to reduce the switching energy of the capacitive digital-to-analog converter (CDAC). The proposed adaptive-reset switching scheme reduces the average switching energy of the CDAC by 90% compared to the conventional scheme without the common-mode voltage variation. In addition, the near-threshold voltage (NTV)-optimized digital library is adopted to alleviate the performance degradation in the ultra-low supply voltage while simultaneously increasing the energy efficiency. The NTV-optimized design technique is also introduced to the bootstrapped switch design to improve the linearity of the sample-and-hold circuit. The test chip is fabricated in a 65 nm CMOS, and its core area is 0.022 mm2. At a supply of 0.5 V and sampling speed of 3 MS/s, the SAR ADC achieves an ENOB of 8.78 bit and consumes $3.09~{\boldsymbol{\mu }}\text{W}$ . The resultant Walden figure-of-merit (FoM) is 2.34 fJ/conv.-step.

A high-efficiency multicharger system for photovoltaic energy harvesting is presented in this letter. The multicharger system is widely used for module-integrated converts to offer a good antipartial shading property. The proposed efficiency-aware cooperative control enhances the total power conversion efficiency of the system (ηTOT) by making chargers help each other when there is a difference between the input powers to each charger due to the partial shading. The system is implemented using a 0.5- μ m CMOS technology. The ηTOT and the power range (for ηTOT > 80%) are improved by 14% (power difference = 1.082 W) and 0.61 W (lower photovoltaic cell power = 43 mW), respectively.

A digital low-dropout regulator (DLDO) with an analogue-assist (AA) loop using a source follower has been proposed to improve the drawbacks of the DLDO. The proposed AA loop, which uses a source follower structure to generate the compensation current without additional passive components, mitigates the voltage droop and accelerates the transient response by complementing a slow digital control loop. Additionally, the boost loop enhances the deceleration of the compensation speed owing to the size of the power transistors. This ultimately results in the improvement of the transient response to the voltage droop side. Also, this can facilitate in reducing the amount of the output capacitance (C OUT) closely associated with the output voltage droop (ΔV OUT). The proposed DLDO occupying an area of 0.015 mm2 is designed in a 28-nm CMOS process. The ΔT s of 14 ns with C OUT of 10 pF is achieved under the load step of 1.5–30 mA with edge time of 2 ns. The consumed quiescent current is 35 μA, and the figure-of-merit of 0.008 ps is achieved.

In this work, a digital phase-locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra-low power consumption adopts the near-threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low-supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time-to-digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma-delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 μA at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz.

A 9 Gb/s/ch transceiver with a reference-less data-embedded pseudo-differential clock signaling (RDCS) for graphics memory interfaces is proposed in a 65-nm CMOS technology. In the RDCS transceiver, the output data is embedded into differential clock signal by adopting a multi-level amplitude modulation in the transmitter (TX), and the data is recovered by extracting the data information from clock signal without reference clock in the receiver (RX) side. Because the data is synchronized with the clock at the TX, the received data can be recovered without DLL in the RX side. In addition, the additional pins required in the graphics memory interfaces can be removed by applying the proposed RDCS. The proposed design achieves less than 10−12 bit error rate with 9 Gb/s/ch data rate, and measured jitter in the recovered clock is 1.42 psRMS. In addition, the power efficiencies of the TX and RX are 2.33 and 1.03 pJ/bit, respectively.

An energy-efficient state-of-charge (SOC) indication algorithm and integrated system for low-power wireless sensor nodes with the miniature Internet of Things (IoT) batteries are introduced in this paper. Based on the key findings that the miniature Li-ion batteries exhibit a fast response to the battery current transient, we propose an instantaneous linear extrapolation (ILE) algorithm and circuit system based on the ILE algorithm allowing accurate on-demand estimation of SOC. Due to the on-demand operation, an always-ON current integration is avoided, reducing power and energy consumption by several orders of magnitude. Furthermore, the proposed SOC indicator does not require a battery disconnection from the load, ensuring continuous operation of the applications. The system is implemented in a 180-nm CMOS technology. The power consumption is 42 nW, and maximum SOC indication error is 1.7%. The minimum applicable battery capacity is as low as $2~\mu $ Ah.

A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a ${\Delta } {\Sigma }$ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth ( $ {f}_{{\text {LBW}}}$ ). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of $ {f}_{\text {LBW}}$ variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest $ {f}_{\text {LBW}}$ . A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2.

Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2 GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty cycle, to mitigate the offset of the BBDCD, an average codes method is used. The operating frequency is determined according to capacitance in the BBDCD for a wide frequency. A duty cycle adjuster (DCA) based on a 2-input NAND gate makes a clock with pulse width from the rising edge of the input clock to the falling edge of the digitally controlled delay line (DCDL) output. The IC is designed in CMOS 28nm process. The maximum duty cycle error of the DCC is 1.5 % at 3.2 GHz. The DCC consumes 1.92 mW at the maximum input frequency. The peak-to-peak jitter of the output clock is 12 ps.

This paper presents a 10-b 1 MS/s SAR ADC with a proposed triple-charge-sharing technique to reduce switching energy. The proposed technique uses an additional reservoir capacitor, which has 10% of total CDAC size, to recycle 56% of switching energy. The energy-saving efficiency of this technique is most noticeable in MSBs, so the number of the MSBs to apply the technique has been optimized. The prototype of the proposed SAR ADC is implemented in a 28 nm CMOS technology at 1 V supply voltage. Logic power is minimized with 0.4 V supply voltage. The proposed SAR ADC consumes 2.02 J.l W and achieves ENOB of 9.15, equivalent to a Walden FoM of 3.55 fJ/conversion-step.

A 1-V 10-Gb/s/pin single-ended transceiver with a controllable active inductor-based output driver and adaptively calibrated cascaded-equalizer with infinite impulse response and finite impulse response filters for a post-LPDDR4 interface in a 65-nm CMOS technology is proposed. The proposed cascaded-equalizer removes the received long-tail inter symbol interference with the help of an IIR filter while the coefficients for the cascaded-equalizer are adaptively calibrated. In addition, the received single-ended ground-terminated data are converted to the differential pair by the proposed input buffer using a calibrated reference voltage. In the transmitter (TX), an output driver with controllable active inductors is proposed to reduce both power consumption and design complexity. At the maximum operating data rate, the measured power efficiencies of TX and receiver are 1.16 and 3.02 pJ/b, respectively, excluding the power dissipation of internal phase locked loop. In addition, the overall active area is 0.0091 mm2.

This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13- $\mu\mbox{m}$ CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.

This paper presents a new energy-efficient ring oscillator collapse-based comparator, named edge-pursuit comparator (EPC). This comparator automatically adjusts the performance by changing the comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. Furthermore, a detailed analysis of the EPC in the phase domain shows improved energy efficiency over conventional comparators even without energy scaling, and wider resolution tuning capability with small load capacitance and area. The EPC is used in a successive-approximation-register analog-to-digital converter (SAR ADC) design, which supplements a 10 b differential coarse capacitive digital-to-analog converter (CDAC) with a 5 b common-mode CDAC. This offers an additional 5 b of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40 nm CMOS shows 74.12 dB signal-to-noise and distortion ratio and 173.4 dB Schreier Figure-of-Merit. With the full ADC consuming 1.17 $\mu \text{W}$ , the comparator consumes 104 nW, which is only 8.9% of the full ADC power, proving the comparator’s energy efficiency.

A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need for a decision feedback equalizer. In order to increase the data sampling margin, the PLL bandwidth is optimized depending on the system noises, which reduces the clock jitter by up to 55.1%. The crosstalk-induced jitter (CIJ) reduction technique suppresses the DQs jitter by employing the suggested training sequence for the GDDR5 interface. Pre- and de-emphasis are merged in one auxiliary driver. This chip operates at 10 Gbits/s/pin and exhibits a data eye opening of 0.78 UI with the CIJ reduction technique. The power consumptions of the TX and RX are 8.28 and 5.5 pJ/b/channel, respectively.

A $4\times 5$ -Gb/s reference-less receiver is proposed in a 0.13- $\mu \text{m}$ CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12- $\mu \text{s}$ locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 ${\rm ps}_{{\mathrm{rms}}}$ , and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.

This brief presents an energy-efficient 10-bit accuracy with 20-kS/s successive approximation register analog-to-digital converter for portable pulse oximeter. A data-dependent capacitor reset (DDCR) switching scheme for the capacitive digital-to-analog converter (CDAC) to reduce the average switching energy and the number of unit capacitors is proposed and implemented. Compared with the conventional capacitor switching scheme for CDACs, the proposed DDCR switching scheme reduces the average switching energy and the total number of unit capacitors by 97% and 75%, respectively. We achieved a signal-to-noise-and-distortion ratio of 56.5 dB and a spurious-free dynamic range of 64.7 dBc at the Nyquist input frequency. The measured peak differential and integral nonlinearities are 0.44 and 0.58 least significant bit, respectively. The figure of merit is 9.1 fJ/conversion-step. The prototype, fabricated in the 0.11- $\mu\mbox{m}$ CMOS process, occupies 0.033 mm2.

An energy efficient State-of-Charge (SOC) indication algorithm and integrated system for small IoT batteries are introduced in this paper. The system is implemented in a 180-nm CMOS technology. Based on a key finding that small Li-ion batteries exhibit a linear dependence between battery voltage and load current, we propose an instantaneous linear extrapolation (ILE) algorithm and circuit allowing on-demand estimation of SOC. Power consumption is 42nW and maximum SOC indication error is 1.7%.

This paper describes the design technique and the method of analog front-end to measure the saturation of hemoglobin with oxygen sensor. To process the SpO2 value from the sensor, the current data from the sensor should be converted into voltage domain. Designed analog front-end usually converts the current data from the sensor into voltage domain data to pass it on analog-to-digital converter called ADC with a different level of gain characteristics. This circuit was fabricated in a 0.11μm CMOS technology and has 4 level of gain properties. The occupied area is 0.174mm.

In this Letter, 400 MHz---1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 psrms at 1.5 GHz operation, and 3.991 psrms at 400 MHz operation. The ADPLL occupies 0.088 mm2, and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.

A rail-to-rail (R-to-R) regulating voltage-controlled oscillator (VCO) is employed to generate multiple-phase clocks for clock and data recovery in a display driver IC (DDI). To achieve a low supply and ground noise sensitivity, the proposed R-to-R regulating method generates VSP and VSN as the supply and the ground of the VCO instead of VDD and VSS. By applying the proposed method, the frequency–VDD variation rate of the VCO (%−f VCO/%−VDD) changes from 3.5%−f VCO/1%−VDD to 0.0073%−f VCO/1%−VDD within the V ctrl range of 0.5–1.2 V. The DDI is fabricated in a 1P6M 0.18 μm 1.8 V CMOS technology for the interface block and in a 1.6 μm 18 V CMOS technology for the DAC. The R-to-R regulating VCO has a tuning range of 140–240 MHz with linear and small gain (K VCO) characteristics, and is suitable for the phase-locked loop used in flat-panel display interfaces that operate from 0.3 to 2 Gbits/s.

A cascaded hybrid phase-locked loop (PLL) fabricated in a 65-nm CMOS process consumes 21 mW and occupies 0.4 mm2. An all-digital PLL (ADPLL) with piecewise linear calibrated hierarchical time-to-digital converter is proposed to achieve a wide operation range, and a charge-pump PLL (CPPLL) with an auxiliary (AUX) charge-pump for low current mismatch is cascaded to filter out the ADPLL output noise. The ADPLL achieves low long-term jitter regardless of the leakage current, and the CPPLL realizes low short-term jitter using a self-biased technique and the AUX charge pump. A phase-selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference constant. The measured peak-to-peak short-term and long-term jitters at an output frequency of 315 MHz are 40 and 70 pspp, respectively, with a multiplication factor of 1024.

A smart temperature sensor in 65-nm CMOS, utilizing CMOS ring oscillators, consumes 1.09 nJ at a conversion rate of 366 kS/s. This is achieved by the direct temperature-to-digital conversion method implemented in the frequency-to-digital converter. The algorithm utilized in the fine code generator makes it possible to increase the resolution of the sensor efficiently. Compared to previous work, this brief shows lower VDD operation. After one point calibration, the chip-to-chip spread is +2.7 ~ -2.9°C over the temperature range of -40°C to 110°C.

This paper presents a temperature sensor based on a frequency-to-digital converter with digitally controlled process compensation. The proposed temperature sensor utilizes ring oscillators to generate a temperature dependent frequency. The adjusted linear frequency difference slope is used to improve the linearity of the temperature sensor and to compensate for process variations. Furthermore, an additional process compensation scheme is proposed to enhance the accuracy under one point calibration. With one point calibration, the resolution of the temperature sensor is 0.18 °C/LSB and the maximum inaccuracy of 20 measured samples is less than ±1.5°C over a temperature range of 0°C ~ 110°C. The entire block occupies 0.008 mm2 in 65 nm CMOS and consumes 500 μW at a conversion rate of 469 kS/s.

We propose a novel modulation profile for a spread spectrum clock generator (SSCG). The proposed piecewise linear (PWL) modulation profile significantly reduces electromagnetic interference with a simple implementation. Two SSCGs with two- and three-slope-PWL modulation profiles are used. Both SSCGs consist of the proposed spread spectrum control profile generator and a phase-locked loop that includes a high-resolution fractional divider to reduce quantization noise from a delta-sigma modulator. The SSCG with the two-slope-PWL modulation profile was fabricated in a 0.18 μm 1P4M CMOS technology. The measured peak power reduction level of the two-slope-PWL modulation profile is 14.2 dB with 5000 ppm down spreading at 1.5 GHz. The SSCG occupies an active area of 0.49 mm2 and consumes 40 mW of power at 1.5 GHz. The SSCG with the three-slope-PWL modulation profile was fabricated in a 0.13 μm 1P6M CMOS technology. The measured peak power reduction level of the three-slope-PWL modulation profile is 10.3 and 10.52 dB with 5000 ppm down spreading at 162 and 270 MHz, respectively. The SSCG occupies an active area of 0.096 mm2 and dissipates 1 mW of power at 270 MHz.

Among the stacked dies using through silicon via (TSV), data conflictions occur due to process mismatches, which decrease the data valid window and consume unwanted power due to the short circuit current. This paper presents the DLL-based data self-aligner (DBDA), which reduces data conflictions among stacked dies. The stacked dies employing the proposed DBDAs automatically align their data output timings without relying on any control signals from the master die or an extra signal among the stacked die. The DBDA reduces the data confliction time (tDC) due to process, voltage and temperature (PVT) variations from 500 ps to 50 ps and thereby reduces the short current from 3.62 mA to 0.41 mA. The proposed DBDA has two operation modes: the synchronous self-align mode (SSAM), in which the data is aligned in the external clock domain and the asynchronous self-align mode (ASAM). The lock time of DBDA is less than 20 cycles in SSAM. Additionally, the lock detector (LD) and proposed re-calibrator help the DBDA to find the optimal calibration period under temperature variation. They also reduce the calibration current of DBDA by 45.5%. A prototype DBDA implemented in 130 nm CMOS technology dissipates 247 μW for 800 Mb/s/pin. For reduction of the leakage current during the power down mode or the self-refresh mode, this paper proposes a leakage current controller, which reduces the leakage power by 90.5%.

Coarse grained arrays (CGAs) with run-time reconfigurability play an important role in accelerating reconfigurable computing applications. It is challenging to design on-chip communication networks (OCNs) for such CGAs with dynamic run-time reconfigurability whilst satisfying the tight budgets of power and area for an embedded system. This paper presents a silicon-proven design of a 64-PE circuit-switched OCN fabric with a dynamic path-setup scheme capable of supporting an embedded coarse-grained processor array. A proof-of-concept test chip fabricated in a 0.13 μm CMOS process occupies a silicon area of 23 mm2 and consumes a peak power of 200 mW @ 128 MHz and 1.2 Vcc, at room temperature. The OCN overhead consumes 9.4% of the area and 18% of the power of the total chip. Experimental results and analysis show that the proposed OCN fabric with its dynamic path-setup is suitable for use in an embedded CGA supporting fast run-time reconfigurability.

This paper presents an Rx only equalization (ROE) technique that eliminates all Tx equalizations to reduce power dissipation, circuit complexity, and cost. The proposed Rx consists of a CTLE, a 1-tap speculative FIR and 2-tap direct IIR DFE. A simpler Tx architecture owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) Tx operation. The proposed Tx consists of dual-mode 2∶1 serializer/pre-drivers and main drivers. The transceiver was fabricated in a 65 nm CMOS technology. The Rx achieves BER < 10−12 over a −22 dB loss PCB channel at 32 Gb/s with 0.62 pJ/b energy efficiency, and occupies 0.024 mm2. The Tx has only 0.77 pJ/b and 0.40 pJ/b energy efficiency at 32 Gb/s in differential mode, and 32 Gb/s/pin in single-ended mode, respectively, and occupies only 0.002 mm2.

This paper presents a new energy-efficient ring oscillator collapse-based comparator, which is demonstrated in a 15-bit SAR ADC. The comparator automatically adjusts comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. The employed SAR ADC supplements a 10-bit differential main CDAC with a 5-bit common-mode CDAC. This offers an additional 5 bits of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40nm CMOS shows 74.12 dB SNDR and 173.4 dB FOMs. The comparator consumes 104 nW with the full ADC consuming 1.17 µW.

This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm2. The measured duty-cycle error for the 50% duty-rate is below 1% (or 10 pS) within 320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.

A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH ΔΣ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of ±0.5% to 3.5% in steps of 0.5% and three modulation frequencies of fm, 2 fm and 3 fm. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 mm2 in a 0.13-μm CMOS process and consuming 23.72 mW at 3.5 GHz.

A 512 Mbit consumer DDR2 SDRAM that uses self-dynamic voltage scaling (SDVS) and adaptive design techniques is introduced in this paper. With the increase in the significance of process variation, higher performance requirements reduce the allowable design margin in DRAM circuits. However, self-dynamic voltage scaling gives a greater timing margin in the circuitry by changing the internal supply voltage in response to the operating frequency and process skew. By changing the internal supply voltage, the life time of the chip increases by more than 23 times when the supply voltage is lowered by 300 mV. The proposed adaptive design techniques include an adaptive bandwidth delay-locked loop and an adaptive clock gating. The former improves the performance by obtaining a wider valid data window and the latter saves on dynamic power consumption in the clock distribution network. The SDVS method reduces the IDD3P by 9.3% and the adaptive clock gating saves 8.8% of the IDD3N when measured at 200 MHz, 25°C The studied consumer DDR2 SDRAM was fabricated using 44 nm standard DRAM process technology. It occupies a 17.7 mm2 die area and operates using a 1.8 V power supply.

A multi-port serial link with wide-range CDR using digital vernier phase shifting and dual-mode control is presented. The proposed vernier phase shifter generates finely-spaced phase steps and provides unlimited phase rotating with a 13.34-ps phase step at 5 Gbps. By inherently digital nature, the vernier phase shifter enables semi-digital dual-loop CDR with precise tracking performance, and with the dual-mode control, the proposed CDR extends the operating range from 250 Mbps to 5 Gbps and achieves a BER of less than 10-12 at 5 Gbps with 29-1 PRBS. Fabricated in a 0.13-μm CMOS process, the main PLL and the single receiver dissipate 9.0 mW and 19.2 mW respectively at 5 Gbps from a 1.2 V supply.

A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and-distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-μm CMOS process, and occupies 1.6 × 0.8 mm2 of active area.

This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The RMS jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm2 in a 0.25-μm 1P5M CMOS technology.

This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply.

This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18-?m CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.1-3.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.

A frequency-to-digital converter based small size smart temperature sensor for portable applications is proposed. To reduce its size and power consumption, the proposed temperature sensor adopted frequency-to-digital converter without relying on a band-gap reference or a voltage/current analog-to-digital converter. The device was fabricated using a 90 nm CMOS process, occupying an area of 0.0018 mm2 with a resolution of 3°C.

A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-mum CMOS process, is presented. A fast lock time of 7.5 mus and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm2 and consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents.

This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 mum CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7 ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.

The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500MHz to 2GHz with ±10% duty ratio error, the output duty ratio error is corrected to be less than ±1.4%. The proposed DCC circuit is designed and verified using a 0.18um CMOS technology.

This paper proposes a cost-effective CMOS optical receiver with a level shifter to reduce pulse width distortion and design complexity in high-definition digital audio interfaces. In this design, a level shifter is introduced at the receiver, in order to improve digital audio quality by threshold convergence. Measurement results demonstrate that the implemented optical receiver in a 0.25-μm CMOS technology can successfully reduce pulse width distortion within ?2% and circuit complexity.

This paper proposes an automatic threshold converged CMOS optical receiver employing a threshold convergence technique to reduce pulse width distortion and design complexity in high-definition digital audio interfaces. A threshold concentrator is introduced at the receiver, in order to improve digital audio quality by aligning various logic thresholds of the input signals into a constant one. Simulation results demonstrate that the designed optical receiver in a 0.18-µm CMOS technology can successfully reduce pulse width distortion within -2% and circuit complexity.

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-mum CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm2 and has a peak-to-peak jitter of plusmn6.6 ps at 1.3 GHz