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The current challenges of spintronic devices are the large power and long latency for magnetic switching. Current-induced domain wall (DW) motion is a new switching mechanism promising low-power, high-density, and high-speed circuits. It was first studied to build “race track” memory, which is considered as one of the most emerging technologies for future stand-alone memory. Based on the 3-D hybrid integration above CMOS circuits and using magnetic tunnel junction (MTJ) as the write/read heads, DW motion can be advantageously extended to logic and embedded memory applications. In this paper, we present the first DW shift register-based lookup-table circuit to build reconfigurable logic, which may nearly halve the die area compared with conventional SRAM-LUT by sharing a number of subcircuits and suggest some new functions such as multicontext configuration and run-time reconfiguration for further performance improvement. By using a DW electrical model and CMOS 65-nm design kit, its performances such as low power and high computing/reconfiguration speed have been simulated or calculated. [ABSTRACT FROM AUTHOR]

Recently, spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising universal memory candidate for future memory and computing systems, thanks to its nonvolatility, high speed, low power, good endurance, and scalability. However, as technology scales down, STT-MRAM suffers from serious process variations and thermal fluctuations, which greatly degrade the performance and stability of STT-MRAM. In general, the optimization and robustness of STT-MRAM under process variations often require a hybrid design flow and multilevel codesign strategies. In this paper, we quantitatively analyze the impacts of process variations and thermal fluctuations on the STT-MRAM performances from physics, technology, and circuit design point of views. Based on the analyses, we found that readability is becoming the newest challenge for deeply scaled STT-MRAM due to the conflict between sensing margin and read disturbance. To deal with this problem, a novel reconfigurable design strategy from device, circuit, and architecture codesign perspective is then presented. Finally, a conceptual hybrid magnetic/CMOS design flow is also proposed for STT-MRAM in deeply scaled technology nodes. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation high-speed, low-power, and scalable nonvolatile memory technology. Its advantageous features have attracted much attention in the area of research and development, and a number of preindustrial prototypes and small-scale products have been demonstrated. One expects to widely commercialize it in the next few years. One of the critical issues that blocks STT-MRAM’s wide commercialization is its low sensing reliability due to the relatively small tunnel magnetoresistance ratio of the magnetic tunnel junction (MTJ) and the continuously increasing process variations, especially as technology process scales down to the deep submicrometer nodes (e.g., 40 nm). In this paper, we present a variation-tolerant high-reliability sensing circuit for deep submicrometer STT-MRAM. This circuit, using triple-stage sensing and charge transfer amplification, is able to tolerate significantly the process variations and improve greatly the sensing margin by sacrificing some sensing time. Using a CMOS 40 nm design kit and a precise STT-MTJ compact model, transient and Monte Carlo simulations have been carried out to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]

Spin transfer torque-based magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates for the next generation of nonvolatile memories; however, its storage density and reliability are currently uncompetitive compared with other nonvolatile memories (e.g., NAND flash). In this paper, a dual-functional memory cell structure, named DFSTT-MRAM, is proposed by stacking multiple magnetic tunnel junctions (MTJs) on top of the CMOS access transistor. In such a structure, the cell can be dynamically configured between two possible functional modes, i.e., high-reliability mode (HR-mode) and multilevel cell mode (MLC-mode), based on the data requirements of the addressed applications. The DFSTT-MRAM cell was electrically modeled based on the perpendicular magnetic anisotropy CoFeB/MgO/CoFeB MTJ integrating the STT stochastic switching behaviors. Transient and Monte Carlo simulations were then performed to evaluate its MLC functionality and reliability performance. Our evaluation results show that the DFSTT-MRAM cell can indeed realize MLC capability providing proper write/read control at the MLC-mode and enhance the intrinsic cell reliability by several orders of magnitude when operating at the HR-mode. This cell structure provides a flexible memory cell design for future advanced applications, such as high-density nonvolatile memory and neuromorphic circuits. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction (MTJ) embedded in complementary metal–oxide–semiconductor (CMOS) has been considered as one of the potentially powerful solutions to build up nonvolatile memory and logic circuits. It possesses many intrinsic merits, such as high speed, instant on/off, good scalability and low-leakage power, and promises to extend the Moore's law. A critical issue in this hybrid MTJ/CMOS structure is the reliable integration of MTJ electric signals to CMOS electronics, especially for the deep submicrometer technology nodes (e.g., 28 nm) in presence of low supply voltage and serious process variations. In this paper, we propose a new sensing amplifier, named separated precharge sense amplifier. This circuit, by separating the discharging and evaluation stages of the sensing operation, can operate at a lower supply voltage (<1.0~V) and reduces the effects of process variations as technology scales, thereby providing higher sensing reliability compared with the previously proposed solutions while preserving the high-speed and low-power consumption. Transient and Monte-Carlo statistical simulations are performed to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]