Search

In this paper, Poisson–Schrödinger simulations of bulk MOSFETs with an InGaAs channel, including traps and nonparabolicity, are compared against experimental data. These simulations are later used to validate a compact model for the inversion charge in the channel as a function of the gate voltage. Finally, an expression for the long-channel drain current is derived from this inversion charge model, and confirmed with experimental data. This current model, adapted for alternative channel devices, is suitable for the evaluation of III–V MOSFET performance. [ABSTRACT FROM PUBLISHER]

In this paper, a model of gate capacitance is proposed for ultrathin-body-BOX and double-gate MOSFETs with light mass channel materials. First, the model is derived by making the assumption that only one subband is occupied and using quantum perturbation theory to compute the corresponding energy level. Next, this model is confirmed with Poisson–Schrödinger simulations. Finally, the impacts in terms of performance and scaling are discussed. [ABSTRACT FROM AUTHOR]

In this paper, the main MOSFET parasitic capacitances of planar devices (i.e., bulk, Fully depleted silicon-on-insulator (FDSOI), and planar double gate) are computed using two successive conformal mapping transforms. First, the structure is mapped to the real axis of the complex plane, and then the second transform, deduced directly from the Schwarz–Christoffel theorem, reduces the capacitance to the trivial parallel electrodes case. This second step involves elliptic integrals, which provide a generic expression for all parasitic capacitances. This method is later compared against other models based on conformal mapping. Finally, the results are validated with finite-element method simulations of the inner and outer fringe capacitances in different architectures, including metallic contacts and raised and faceted junctions. [ABSTRACT FROM AUTHOR]

In this paper, the boundary conditions at the edges of the junctions are discussed, and their consequences on the compact modeling of short-channel effects (SCEs) in MOSFETs are investigated. It is first shown that the previous voltage-doping transform (VDT) potential model does not agree with the simulation results when the impact of lightly doped drain regions or thin spacers are considered. A solution is then proposed to correct the channel potential model using more accurate boundary conditions at the edges of the channel, which consist in calculating an accurate effective built-in potential value Vbi^\rm eff at the source and at the drain. The impact of these improved boundary conditions on compact models of SCEs is investigated. It is shown that the previous VDT models of drain-induced barrier lowering and subthreshold swing for all types of fully depleted devices can be very simply corrected to finely agree with the simulations without fitting parameters. These models finally allow to investigate the impact of the doping concentration of the junctions on the device performance. [ABSTRACT FROM PUBLISHER]