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This paper presents the design of a 4-bit switched attenuator operating in the frequency range of DC to 8 GHz band. The attenuator is fabricated using a 28-nm bulk CMOS process for verification. The designed attenuator employs switched T-type and π-type structures, with a simplified π-type circuit to reduce size for the 0.5 dB bit. Additionally, an inductor is added between the 0.5 dB bit and the 1 dB bit to improve input and output matching. Measured input and output return loss in the frequency band of DC to 8 GHz is greater than 11.45 dB, insertion loss is less than 2.69 dB, the measured RMS gain error is less than 0.64 dB, and the RMS phase error is less than 1.42°. The actual size of the attenuator, excluding the RF and DC pads, is 0.236×0.146 mm². [ABSTRACT FROM AUTHOR]

This paper discusses the design of a driver amplifier operating in the Ku-band using a 130 nm SOI CMOS process. The amplifier consists of two stages: a cascode amplifier in the first stage for high gain, and a CS amplifier in the final stage for high OP1dB. In the cascode amplifier structure of the first stage, a series inductor is added between the CS and CG amplifiers to simplify input matching. This modification shifts the maximum Gm point of the cascode amplifier to a lower frequency, resulting in a high gain at the target frequency. The measured amplifier achieves a maximum gain of 13.7 dB and an OP1dB of −0.3 dBm. It consumes 12 mW of power at 1.2 V and occupies an area of 0.188 mm², excluding the DC and RF pads. [ABSTRACT FROM AUTHOR]

This paper presents the design of W-band Wilkinson power divider using 65 nm bulk CMOS process. In this design, the quarter-wavelength (λ/4) transmission line was replaced with a lumped element, and a CRC structure was applied to the isolation network circuit. In addition, a metal wall was installed between the two output lines to enhance isolation. This power divider had a maximum insertion loss of 1.93 dB and a minimum isolation of 13.3 dB in the 75~110 GHz band. The return loss was more than 7.2 dB, and the size of the core was 0.2×0.12 mm². [ABSTRACT FROM AUTHOR]

This study presents a Q-band wideband low-noise amplifier (LNA), which is implemented and verified using a 65-nm bulk CMOS process, for millimeter-wave applications. The proposed low-noise amplifier uses a transformer structure at the input stage to obtain broadband input-matching characteristics. Under 1-V supply voltage, the proto-type LNA achieves a simulated peak gain of 22.74 dB with gain variation of ±0.37 dB in frequency band. The simulated noise figure (NF) was 3.27 dB at 40 GHz while consuming 17 mW. The core occupies an area of 0.13 mm². [ABSTRACT FROM AUTHOR]

This study entailed the development of a K-Band power amplifier (PA). The proposed PA was implemented and verified using a 65-nm bulk CMOS process. The PA was designed with two stages to obtain sufficient gain in the K band. The PA had a chip area of 0.93×0.47 mm² including RF and DC pads. The manufactured power amplifier design had a maximum saturation power of 22.4∼22.7 dBm in the 19–21 GHz frequency band, and a power added efficiency (PAE) of 39 %∼40 %. In the two-tone simulation results, the linear power and efficiency levels satisfying third-order inter-modulation distortion (IMD3) below −30 dBc were confirmed to be 16∼17 dBm and 24%∼26 % in the 19∼21 GHz frequency band, respectively. [ABSTRACT FROM AUTHOR]

This study entailed the design of a K-band low noise amplifier (LNA) by using the 65-nm bulk CMOS process. In the designed low noise amplifier, a large transistor was used to reduce the size of the lossy gate series inductor, resulting in low noise and high gain. In addition, the source generation and shunt inductors were used at the input stage to enable simultaneous noise and input matching. The LNA had a size of 0.67×0.39 mm² including RF and DC pads. A peak gain of 19.5 dB and a minimum noise figure of 2.31 dB were achieved. Owing to the design, the input and output return loss was more than 10 dB at 17∼23 GHz. [ABSTRACT FROM AUTHOR]