1. A Low-Jitter and Low-Spur Charge-Sampling PLL.
- Author
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Gong, Jiang, Charbon, Edoardo, Sebastiano, Fabio, and Babaie, Masoud
- Subjects
VOLTAGE-controlled oscillators ,PHASE detectors ,PHASE-locked loops ,PHASE noise ,COMPLEMENTARY metal oxide semiconductors ,PARTIAL discharges - Abstract
This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50- $\mu \text{W}$ RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm2 and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW. [ABSTRACT FROM AUTHOR]
- Published
- 2022
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