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High peak and average efficiency is an important feature of power amplifiers (PAs) for 5G millimeter-wave communication. This article reviews the challenges of conventional outphasing approaches in CMOS technologies and demonstrates a low-loss outphasing combiner for low loadline impedance. Undesirable characteristics of CMOS devices for outphasing are compensated with neutralization, unilaterization, and stabilization networks for the outphasing PA (OPA). The OPA is realized in 45-nm CMOS silicon on insulator (SOI) and demonstrates 40% 6-dB backoff drain efficiency (DE) while providing 17-dBm peak output power with a peak 50.5% DE. For 64-QAM, a 31.3% average DE and 10.1-dBm average output power are measured. The OPA demonstrates less than 1.5% error vector magnitude (EVM) with 64-QAM waveform using a phase-based lookup table (LUT). With 16-QAM, the bit rate reaches 20 Gb/s with 12% EVM. To the best of our knowledge, this is the highest bit rate for a high-efficiency PA. The adjacent channel leakage ratio (ACLR) is under −25 dBc. [ABSTRACT FROM AUTHOR]

Two $K_{u}$ - to V-band distributed amplifiers (DAs) based on nMOS and nMOS/pMOS gain stages and a distributed transceiver front end (DTFE) are presented for ultra-wideband power and low-noise amplification in a 45-nm RF CMOS silicon-on-insulator (SOI) technology. Supply scaling of gain stages through high-pass filter sections achieves high efficiency while maintaining a broadband 50- $\Omega $ match. The nMOS DA has a gain of 13 dB over a 3-dB bandwidth of 10–82 GHz and a minimum noise figure (NF) of 5.3 dB. The measured peak output power is 17.2 dBm with a peak power-added efficiency (PAE) of 17.4% at 50 GHz. The hybrid DA allows higher operating voltage and distortion cancelation of scaled pMOS devices to an achieve output power of 17.5 dBm with PAE of 20.2% and low third-order intermodulation and amplitude–phase nonlinearities. The DTFE utilizes time-domain duplexing to drive a shared antenna port for transmit (TX) and receive (RX) modes. It achieves TX gain of 11.7 dB from 12–76 GHz with peak output power of 17 dBm and PAE of 14.2%. RX gain is 9 dB from 11–77 GHz with a minimum NF of 6.2 dB. The 5-GHz wideband 16-QAM is demonstrated in the amplifier circuits for data rates exceeding 20 Gb/s. [ABSTRACT FROM AUTHOR]

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

A fully integrated CMOS power amplifier (PA) that efficiently generates high-voltage RF waveforms directly from a 4.8-V supply using only low-voltage thin-oxide transistors is introduced. High-voltage operation is achieved via implicit ~100% efficient dc–dc conversion enabled by stacking and flying individual class-D PA cells in a House-of-Cards (HoC) topology. By dynamically reconfiguring digitally controlled HoC slices to support different voltage conversion ratios and capacitively coupling their outputs, a Doherty-like high-efficiency backoff profile is achieved without using any magnetic impedance inverter. A test chip, implemented in 65-nm low-power CMOS, operates directly from 4.8 V using only 1.2-V transistors, and attains above 40% battery-to-RF efficiency at both 23-dBm peak power and at 6-dB backoff at 720 MHz. When applying a 10-MHz 16-quadrature amplitude modulation signal, the PA achieves an error vector magnitude of 3.6%-rms without using any predistortion techniques with an average output power and power-added efficiency of 15.7 dBm and 26.5%. [ABSTRACT FROM AUTHOR]

Double-edged pulsewidth modulation (DPWM) is less sensitive to frequency-dependent losses in electrical chip-to-chip interconnects. However, the DPWM scheme instantaneously transmits information at a different rate than a synchronous source. This paper presents an 8-/9-bit line-coding scheme to compensate for the timing skew between the DPWM and synchronous clock domains while limiting the size of buffering required in the transmitter and receiver. Furthermore, preemphasis is introduced and analyzed as a means to improve the signal integrity of a DPWM signal. A multiphase-based, time interleaving receiver architecture using a sense amplifier is presented for high-speed data recovery. The DPWM transceiver is implemented in a 45-nm CMOS Silicon on insulator and operates at 10 Gbit/s with 10^-12 bit error rate and consumes 96 mW. The power consumption of the 8-/9-bit coding hardware is 1.5 mW at 10 Gbit/s demonstrating low-power overhead. [ABSTRACT FROM AUTHOR]

A 10-GHz outphasing modulator is implemented in a 45-nm CMOS silicon-on-insulator process. The modulator is designed to provide high linearity and can operate at high data rates by using 256-QAM while maintaining low error vector magnitude (EVM). Four high-speed 10-bit digital-to-analog converters (DACs) are integrated with dual in-phase and quadrature upconverters. To deliver high output power to an off-chip power amplifier, stacked field-effect transistor current buffers are used to isolate the modulator from the load and mitigate device breakdown. As a result, this modulator delivers 23 dBm to a differential 100-\Omega load. The high-resolution DACs provide a fine control of the phase between the outphased signals and support more than 60 dB of dynamic range and power steps smaller than 1 dB over the entire output power range. The outphasing modulator demonstrates an EVM of 2.2% at 80 Mbit/s and an EVM of 3.4% at 1.1 Gbit/s for 256-QAM. To our knowledge, this is the first demonstration of an outphasing modulator operating above 1 Gb/s. [ABSTRACT FROM PUBLISHER]

This paper presents a reconfigurable dual Q- and W-band bidirectional amplifier and a V-band active circulator in a 45-nm CMOS silicon-on-insulator (SOI) technology. The circuits rely on reconfigurable feedback networks to manipulate the traveling wave along a transmission line. The dual Q- and W-band bidirectional amplifier operates at 40 and 81 GHz, with peak gain of more than 4.2 dB in all modes of operation. The V-band active circulator is reconfigurable to operate in four different modes of operation: clockwise, counter-clockwise, quasi-circulation, and as a thru between port 1 and port 2. The circulator is measured to have an insertion loss of 7.4 dB with isolation between any pair of isolated ports better than 18 dB from 62-75 GHz. The circuit technique proposed here can easily be adapted to operate at different millimeter-wave frequency bands. [ABSTRACT FROM AUTHOR]

A 10 bit current-steering, digital-to-analog converter (DAC) is presented that delivers 6 VPP into a 100 Ω differential load. To realize high-voltage swings using fineline CMOS, a stacked-FET buffer is used to isolate the current source from the output load. The stacked-FET buffer degrades the linearity of the DAC. This work presents a Volterra analysis to capture the frequency-dependent behavior of the stacked-FET circuit that can be cascaded to quantify the linearity of an N-device stack. The power DAC is implemented in 45 nm CMOS SOI and the measured differential nonlinearity (DNL) and integral nonlinearity (INL) is better than 0.4 and 0.6 LSB, respectively. The DAC consumes 476 mW and achieves a peak SFDR of 73 dB and a minimum IM3 of -69 dBc. This DAC demonstrates the largest output swing and highest power efficiency for a high-resolution (>8 bit), high-speed (>100 MS/s) DAC. [ABSTRACT FROM PUBLISHER]

This paper presents an analog circuit scheme to steer phased-array receivers in the direction of an incoming signal. The proposed circuit technique utilizes a coupled-oscillator array along with a coupled-phased-locked loop to auto-align an N-element receive array towards the direction of the incident RF signal. A four-element receiver array is implemented in 45-nm CMOS SOI process and achieves auto-steering range of \pm 35^\circ from broadside. A three-element version of the array demonstrates higher auto-steering angle covering \pm 70^\circ range. The receiver also performs signal demodulation for the incident modulated RF signal, allowing high-data rate communication. A 60-Mbps 64-QAM modulated RF signal is demodulated with error-vector-magnitude (EVM) less than 4% across the steering angle range. The chip area is 3.45 mm^2 including a pad frame with 30-mW/element power consumption. To the best of authors' knowledge, this is the first demonstration of an analog self-steering array in an integrated circuit. [ABSTRACT FROM AUTHOR]

A 45 GHz active phase-shift Doherty PA is proposed and implemented in 45-nm SOI CMOS. The quarter wave-length transmission line at the input of the auxiliary amplifier is replaced by an amplifier, increasing the gain and PAE by more than 1 dB and 5%, while reducing the die area. Use of slow-wave coplanar waveguides (S-CPW) improves the PAE and gain by approximately 3% and 1 dB, and further reduces the die area. Two-stack FET amplifiers are used as the main and auxiliary amplifiers, allowing a supply voltage of 2.5 V and increasing the output power. The active phase-shift Doherty amplifier demonstrates a peak power gain and PAE of 8 dB and 20% at 45 GHz. It occupies 0.45 mm^2, and at 6-dB back-off power, the PAE is 21%. [ABSTRACT FROM AUTHOR]

This paper presents passive integrated circuits for millimeter-wave transmitters and receivers implemented in a 45-nm CMOS silicon-on-insulator (SOI) process. The advantages of SOI over bulk CMOS are discussed for millimeter-wave passive circuits. First, a single pole double throw (SPDT) switch demonstrates a measured insertion loss of less than 1.7 dB at 45 GHz and third-order intermodulation intercept point (IIP3) of 18.2 dBm. Second, a double-balanced passive in-phase/quadrature (I/Q) mixer exhibits a conversion loss of 8.35 dB at 44 GHz and IIP3 of 15.5 dBm. At a fixed IF of 200 MHz, the minimum I/Q gain and phase imbalance is 0.25 dB and 1.9^\circ. The passive mixer and SPDT switch results demonstrate a record minimum insertion loss and linearity performance for the passive millimeter-wave circuits. [ABSTRACT FROM AUTHOR]

This paper presents a pulse-compression radar baseband analog signal processing integrated in a silicon process for low cost and power dissipation. The analog signal-processing circuitry exhibits the autocorrelation properties of the polyphase codes, maximizes the sensitivity and resolution of a pulse radar system, and alleviates speed and resolution requirements of the analog-to-digital converter (ADC) via an analog correlator. The circuitry includes a two-stage variable gain amplifier (VGA) for high dynamic range, a correlator/integrator circuit, a comparator, and offset calibration circuits. The differential 6-bit VGA is designed to adaptively track the Friis path loss through rapid change of the VGA gain and offset calibration, relaxing the dynamic range requirements of the correlator. The measured performance shows a VGA gain variation of 52 dB and a VGA group-delay imbalance of 50 ps over 64 states. The high-speed pulse compression/correlation is performed in analog current domain and the speed requirement on the ADC is reduced by a factor equal to the duty cycle lowering the ADC power consumption. The chip is fabricated in a 90-nm process, wire bonded on the FR4 printed circuit board, and tested with a Stratix IV field-programmable gate-array board to evaluate the system performance for different radar polyphase codes. [ABSTRACT FROM AUTHOR]

The performance of high-efficiency millimeter-wave (mm-wave) power amplifiers (PAs) implemented in a 45-nm silicon-on-insulator (SOI) process is presented. Multistage class-AB designs are investigated for Q- and W-bands and a push–pull amplifier is investigated at Q-band. The Q-band, class-AB PA achieves a saturated output power of 15 dBm and power-added efficiency (PAE) of 27% from a 2-V supply. The W-band, class-AB PA achieves a saturated output power of 12.4 dBm and PAE of 14.2% from a 2-V supply. The performance demonstrates the high efficiency possible for mm-wave PAs in a SOI process. [ABSTRACT FROM PUBLISHER]

A low-power, 40-Gb/s optical transceiver front-end is demonstrated in a 45-nm silicon-on-insulator (SOI) CMOS process. Both single-ended and differential optical modulators are demonstrated with floating-body transistors to reach output swings of more than 2\,VPP and 4\,VPP, respectively. A single-ended gain of 7.6 dB is measured over 33 GHz. The optical receiver consists of a transimpedance amplifier (TIA) and post-amplifier with 55 dB\cdot\Omega of transimpedance over 30 GHz. The group-delay variation is \pm 3.9 ps over the 3-dB bandwidth and the average input-referred noise density is 20.5 \pA/\sqrt\Hz. The TIA consumes 9 mW from a 1-V supply for a transimpedance figure of merit of 1875 \Omega/pJ. This represents the lowest power consumption for a transmitter and receiver operating at 40 Gb/s in a CMOS process. [ABSTRACT FROM AUTHOR]

A broadband amplifier is realized with cascaded stagger-tuned stages that are equalized for high bandwidth and low gain ripple. The staggered frequency response is demonstrated to improve the transimpedance limit of active circuits. The staggered response is demonstrated with a Darlington feedback amplifier and a constructive wave amplifier, which achieves low group delay. The broadband amplifier is implemented in a 0.12-\mu\ m SiGe BiCMOS process and achieves a 3-dB bandwidth of 102 GHz. The gain is 10 dB with 1.5-dB gain-ripple and group-delay variation under \pm6 ps over the entire 3-dB bandwidth. The chip occupies an area of 0.29 \ mm^2 including the pads and consumes 73 mW from a 2-V supply. [ABSTRACT FROM PUBLISHER]

A dual-channel CMOS distributed amplifier (DA) is proposed for a highly linear receiver front-end. Proper choice for the number of stages and cutoff frequency of the distributed circuit realizes isolation between amplifier channels. Analysis of the distributed circuit describes the role of reverse gain in minimum noise figure (NF) and intermodulation distortion. The chip is fabricated in a \0.13-\mu\ m CMOS process, occupies an area of \ 0.60 mm^2, and consumes 18 mW from a 1.2-V supply. Measurements of the DA show an NF of 5.7 dB, an output P1~{dB} of 4.9 dBm, and a forward gain of 9.6 dB at 24 GHz. [ABSTRACT FROM AUTHOR]

A millimeter-wave rotary-wave oscillator (RWO) is presented that hybridizes standing- and traveling-wave behavior. This paper presents an analysis of the phase noise of this RWO. The multiphase voltage-controlled RWO is implemented in a 0.12-\mu\ m SiGe BiCMOS process using only nMOS devices for the oscillator core. The measured frequency of operation is 45 GHz with 6.5% tuning range and has a phase noise of -\91 dBc/Hz at 1 MHz and -\112 dBc/Hz at 10 MHz. The power consumption of the oscillator core is 13.8 mW from a supply voltage of 1.2 V. [ABSTRACT FROM AUTHOR]

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for inter-symbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6 Gb/s and 600 mVpp output swing, a power budget of 3 mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24 mW, a budget of 4 mW/Gb/s. [ABSTRACT FROM AUTHOR]

We present a method for predicting data-dependent jitter (DDJ) introduced by a general linear time-invariant LTI system based on the system`s unit step response. We express the exact DDJ of a first-order system and verify the validity of the solution experimentally. We then propose a perturbation technique to generalize the analytical expression for DDJ. We highlight the significance of the unit step response in characterizing DDJ and emphasize that bandwidth is not a complete measure for predicting DDJ. We separate the individual jitter contributions of prior bits and use the result to predict the DDJ of a general LTI system. In particular, we identify a dominant prior bit that signifies the well-known distribution of deterministic jitter, the two impulse functions. We also show a jitter minimization property of high-order LTI systems. We verify our generalized analytical expression of DDJ for several real systems including an integrated CMOS 10-Gb/s trans-impedance amplifier by comparing the theory and measurement results. The theory predicts the jitter with as low as only 7.5% error. [ABSTRACT FROM AUTHOR]