Search

CMOS downscaling makes advanced memory and computing systems more vulnerable to radiation. Emerging non-volatile memories such as Magnetic RAM (MRAM) are under development to replace SRAM and FLASH memories. Spin Transfer Torque Magnetic Memory (STT-MRAM) is considered as one of the most promising memories for high reliability applications. This is due to its intrinsic hardness to radiation, as storage is based on the spin direction of electrons instead of the charge. Its peripheral CMOS circuits are sensitive to radiation; however we can recharge frequently the non-volatile storage to get correct data. Different from conventional MRAM based on magnetic field switching, STT-MRAM is unable to be used directly for hard radiation applications as the current pulses induced by radiation may change the storage due to the stochastic behaviors of spin transfer torque mechanism. In this paper, we analyze firstly this issue and propose a rad-hard design for STT-MRAM sensing circuit with low area overhead and negligible performance degradation. Both transient and Monte-Carlo simulation have been performed to demonstrate its performance and behaviors. [ABSTRACT FROM PUBLISHER]

Magnetic tunnel junction (MTJ) embedded in complementary metal–oxide–semiconductor (CMOS) has been considered as one of the potentially powerful solutions to build up nonvolatile memory and logic circuits. It possesses many intrinsic merits, such as high speed, instant on/off, good scalability and low-leakage power, and promises to extend the Moore's law. A critical issue in this hybrid MTJ/CMOS structure is the reliable integration of MTJ electric signals to CMOS electronics, especially for the deep submicrometer technology nodes (e.g., 28 nm) in presence of low supply voltage and serious process variations. In this paper, we propose a new sensing amplifier, named separated precharge sense amplifier. This circuit, by separating the discharging and evaluation stages of the sensing operation, can operate at a lower supply voltage (<1.0~V) and reduces the effects of process variations as technology scales, thereby providing higher sensing reliability compared with the previously proposed solutions while preserving the high-speed and low-power consumption. Transient and Monte-Carlo statistical simulations are performed to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]

A new path to frame low power, high-density and fast integrated circuits has been rolled out by the observation of current-induced domain wall (DW) motion in magnetic track. As an advanced extension of this mechanism, high performance racetrack memory can be built up combining with magnetic tunnel junction (MTJ) read and write heads. The rapid progress of CoFeB/MgO perpendicular magnetic anisotropy (PMA) shows that the PMA MTJ can be scaled down to 20 nm while keeping fast data access. These recent discoveries allow us to design an ultra-high density content addressable memory (CAM), one of the most important applications of MRAM. The mainstream CAMs suffer from high power and large area as its conventional structure is composed of numerous large-capacity SRAM blocks in order to provide fast data access. MRAM based non-volatile CAMs have been proposed to relive the power consumption, however the density issue cannot be surmounted due to the large switching currents. In this paper, we present a design of NOR-type CAM based on DW motion in PMA magnetic tracks. The CMOS switching and sensing circuits are globally shared to optimize the cell area down to 6 F^2/bit; the complementary dual track allows the local sensing and faster data search speed while keeping low power. By using an accuracy spice model of PMA racetrack memory and CMOS 65 nm design-kit, mixed simulations have been performed to demonstrate its functionality and evaluate its high performance. [ABSTRACT FROM PUBLISHER]

Magnetic RAM (MRAM) is considered as a promising nonvolatile memory technology for aerospace and avionic electronics thanks to its intrinsic hardness to radiation. Data is stored on the spin direction “up” and “down” of electrons instead of positive and negative charge. Thanks to its fast speed, easy integration with CMOS and infinite endurance, MRAM has been proposed to build up nonvolatile latches and logic circuits to overcome the power challenge of conventional CMOS circuits. However, they are vulnerable to single event effects (SEE) due to their CMOS peripheral circuits. Hardening techniques to mitigate SEE are described in this paper. A new design of Radhard MRAM latch is firstly presented. TMR technique is then implemented on configurable logic block (CLB) to mitigate SET on data paths. By using 65 nm design kit and an MRAM compact model, hybrid simulations have been done to demonstrate the radiation hardness and performance. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design. [ABSTRACT FROM AUTHOR]

Recently, ultra-low power circuits based on logic-in magnetic tunnel junction (MTJ) memory structure have been studied thanks to its non-volatility, infinite endurance, high access speed, and easy integration with CMOS process. However, this type of circuit suffers from low reliability both in memory cell and sensing amplifier circuits, which greatly limits its practical applications for logic computation. In this paper, we present a new design of magnetic full adder (MFA) to overcome this issue based on the thermally assisted switching (TAS) MTJ cell and pre-charge sensing amplifier (PCSA) circuit. By using CMOS 65 nm design kit and a precise TAS-MTJ model, mixed simulations have been performed to demonstrate its high reliability keeping low power and small die area. [ABSTRACT FROM PUBLISHER]

The current challenges of spintronic devices are the large power and long latency for magnetic switching. Current-induced domain wall (DW) motion is a new switching mechanism promising low-power, high-density, and high-speed circuits. It was first studied to build “race track” memory, which is considered as one of the most emerging technologies for future stand-alone memory. Based on the 3-D hybrid integration above CMOS circuits and using magnetic tunnel junction (MTJ) as the write/read heads, DW motion can be advantageously extended to logic and embedded memory applications. In this paper, we present the first DW shift register-based lookup-table circuit to build reconfigurable logic, which may nearly halve the die area compared with conventional SRAM-LUT by sharing a number of subcircuits and suggest some new functions such as multicontext configuration and run-time reconfiguration for further performance improvement. By using a DW electrical model and CMOS 65-nm design kit, its performances such as low power and high computing/reconfiguration speed have been simulated or calculated. [ABSTRACT FROM AUTHOR]