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In this paper, a passive half-quadrature hybrid (HQH) is presented for multiphase signal generation at radio frequencies. Utilizing capacitance ratios as the primary design parameters, the proposed hybrid exhibits excellent magnitude and phase balance even in the presence of process and temperature variations. Therefore, it is well suited for integrated-circuit designs with on-chip capacitive elements. Using a standard 0.18-\mu\ m CMOS process, the HQH circuit is integrated with a 5.6-GHz quadrature voltage-controlled oscillator (QVCO) and four down-conversion mixers for demonstration. As the QVCO oscillation frequency sweeps from 5.4 to 5.8 GHz, the measurement results indicate a root-mean-square (rms) magnitude error less than 0.5 dB and an rms phase error ranging from 4^\circ to 7^\circ at the half-quadrature outputs without any feedback correction. [ABSTRACT FROM PUBLISHER]

This paper presents experimental CMOS RF frontends suitable for ultra-low-power and ultra-low-voltage operations. In order to achieve the desirable gain and linearity of the receiver chain at a reduced supply voltage, the current-reused bias technique and the multiple-gated transistors are employed. As for the transmitter frontend, a low-voltage double-balanced mixer is utilized to maximize the conversion gain. In addition, a differential-to-single-ended circuit is also included to increase the saturated output power. Using a standard 0.18-\mum CMOS process, the proposed circuits are realized for 5-GHz RF applications with a supply voltage of 0.6 V. The fabricated receiver frontend demonstrates a conversion gain of 14.5 dB and an IIP3 of - 16 dBm with a power consumption of 2.1 mW, while the conversion gain and the output 1-dB compression of the transmitter frontend are 12.9 dB and -4.1 dBm, respectively, provided a dc power of 6 mW. [ABSTRACT FROM PUBLISHER]

In this paper, a novel circuit topology of aCMOS divide-by-4 direct injection-locked frequency divider is presented for millimeter-wave applications. To enhance the locking range for circuit operations with a division ratio of 4, a series peaking technique is introduced in the proposed divider structure such that improved input injection efficiency can be achieved. Using a standard 0.18-\mu\ m CMOS process, a V-band frequency divider is fabricated for demonstration. Operated at a supply voltage of 1.8 V, the divider core consumes a dc power of 12.6 mW. At an incident power of 0 dBm, the fabricated circuit exhibits an input locking range of 2.44 GHz in the vicinity of 60 GHz. The measured output power and locked phase noise at 1-MHz offset are -\7 dBm and -\133 dBc/Hz, respectively. [ABSTRACT FROM AUTHOR]