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The physical effects that must be included in an accurate model of a silicon-controlled rectifier are discussed and compared with those for bipolar transistors. There are key differences in the modeling of the intrinsic silicon resistances and current gain for the two devices. Proper modeling of the underlying physics results in a compact model that is applicable over a wide range of current levels and is scalable. [ABSTRACT FROM AUTHOR]

Abstract: A model is presented for external latchup. The effects of spacing, temperature, supply voltage and layout are captured in the model. The model shows a good fit to measurement results from two different technologies, RF-CMOS and SmartMOS. [Copyright &y& Elsevier]

Two 3.65-mW, ESD-protected, BiCMOS ultra-wideband low-noise amplifiers (LNAs) for operation up to 10 GHz are presented. These common-base LNAs achieve significant savings in die area over more widely used cascoded common-emitter LNAs because they do not use an LC input matching network. A design with a shunt peaked load achieves a high S21 (17-19 dB) and low noise figure (NF) (4-5 dB) across the band. A resistively loaded design exhibits a lower S21 (15-16 dB) and higher NF (4.5-6 dB), but also utilizes 20% less silicon area. Both LNAs achieve a 1.5 kV ESD protection level and an acceptable S11 (<-10 dB) across the band. Current source noise reduction is critical in common base topologies. Therefore, detailed noise analyses of MOS- and HBT-based current sources are provided. [ABSTRACT FROM AUTHOR]

Design guidelines for static and domino silicon-on-insulator (SOI) CMOS circuits are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-silicon. Most published design fixes for eliminating parasitic bipolar induced upset are shown to aggravate the charge sharing problem. A new and improved predischarge method for enhancing the noise tolerance of SOI domino circuits is thus proposed. The topic of multiple output domino logic in SOI technology is addressed for the first time. Multiple output domino logic is shown to be more prone to bipolar leakage induced upset than regular domino. Many of the design practices used to alleviate bipolar leakage in regular domino are no longer valid due to the multiple output domino logic's inherent design requirements. A novel SOI-specific multiple output domino logic, particularly suitable for adder designs, is introduced to minimize the bipolar leakage risk. [ABSTRACT FROM AUTHOR]

Presents an electromigration reliability diagnosis tool (iTEM) for complementary metal oxide semiconductor (CMOS) very-large scale integration (VLSI) circuits. Temperature effect on electromigration reliability; Block diagram of iTEM; Results of electrothermal timing simulation.