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This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy2O3 cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 Å Dy2O3 cap resulting in ΔeWF ≈ 400 meV and final eWF ≈ 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the VT uniformity, gate leakage, mobility, and reliability. Wellbehaved short-channel devices (Lg ∼ 100 nm, SS ∼ 70 mV/dec, and DIBL ∼ 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy2O3 cap (5 Å)] devices with NiSi-FUSI gates, corresponding to a similar Tinv (ΔTinv < 1 Å). This capping approach, when combined with Ni-silicide FUSI phase engineering, allows ΔeWF(n-p) values up to ∼800 meV, making it promising for low-VT CMOS. [ABSTRACT FROM AUTHOR]

Abstract: This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (eWF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: (a) deposition of a Dy2O3 capping layer on the host dielectric (SiON or HfSiON), or (b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: (1) both cases result in dielectric modification with gate leakage (J G) reduction; (2) adding a cap has no significant impact on T inv(<1Å), while up to ∼5 and 2Å reduction occurs for SiON and HfSiON Yb-implanted devices, respectively, (3) the largest J G reduction (150×) is obtained for capped SiON devices due to dielectric intermixing and formation of a new high-k dielectric (DySiON), comparable to HfSiON in J G and mobility but with 500mV smaller V T; (4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; (5) excellent process control and reliability behavior (V T instability by a.c. pulsed IV, PBTI and TDDB) is reported for both eWF tuning methods. They allow ΔeWF(n−p) values up to ∼800meV when combined with Ni–silicide FUSI phase engineering, promising for low-V T CMOS. [Copyright &y& Elsevier]