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A new deep learning (DL)-based parameter extraction method is presented in this brief; 50k training cases are generated by Monte Carlo simulations of these preselected parameters in Berkeley short-channel IGFET model (BSIM)-common multigate (CMG). DL models are trained using backward propagation with ${C} _{\text {gg}} - {V} _{g}$ and ${I} _{d} - {V} _{g}$ as the input and selected BSIM-CMG parameters as the output. A TCAD simulated FinFET device, calibrated to Intel 10-nm node, is used to test the DL models. The DL-based parameters extraction results show an excellent fit to capacitance and drain current data, with 0.16% rms error in ${C} _{\text {gg}} - {V} _{g}$ and 6.1% rms error in ${I} _{d} - {V} _{g}$ (0.69% rms error in above-threshold-voltage ${I} _{d} - {V} _{g}$), respectively. In addition, devices with a 10% variation in gate length and oxide thickness are successfully modeled with the trained DL model. The results show tremendous promise in using the DL-based models for parameter extraction. [ABSTRACT FROM AUTHOR]

In this letter, we present a compact model of ferroelectric field-effect-transistor (FEFET). The model consists of a ferroelectric (FE) capacitor model and a Berkeley Short-channel IGFET Model (BSIM), a standard SPICE MOSFET model. The FE model, similar to the nucleation-limited-switching model, is based on the statistical multidomain dynamics of FE materials. The charge equality between FE and MOSFET is satisfied through the SPICE simulator. The model reproduces the steep switching in the reverse bias region observed in experimental FEFETs and the current drop at both major loop and minor loop switching. A versatile inverted-memory-window (IMW) model can model the IMW behavior of FEFET that may be caused by charge trapping. We demonstrate that the reported model can accurately fit the published data of Fin-FEFET and FDSOI-FEFET under different bias conditions. [ABSTRACT FROM AUTHOR]

In this article, we present a compact model of metal–ferroelectric (FE)–insulator–semiconductor (MFIS) tunnel junction. Unlike the metal–FE–metal (MFM) structure with only one insulator layer, MFIS–FE tunnel junction (FTJ) contains two insulator layers and a semiconductor electrode. The complex structure makes it difficult to self-consistently solve the Poisson and charge equations. We report the first compact model of MFIS-FTJ to our knowledge. Previous modeling studies focused on numerical simulation, which is time-consuming and not applicable to circuit simulation. The presented compact model is suitable for commercial SPICE IC simulation. It includes a FE model that can capture polarization switching under arbitrary applied voltage, an insulator–semiconductor model that calculates the potential profile of the MFIS stack, and an analytical tunneling current model. We demonstrate that this model can be used to simulate and fit both n-type and p-type MFIS-FTJs. [ABSTRACT FROM AUTHOR]

We present a compact model of polycrystalline ferroelectric (FE) capacitors. The polycrystalline thin-film material is modeled as a collection of independent grains or grain groups. Each grain or grain group is characterized by its local field-dependent switching rate, which is characterized by a distribution function such as Gaussian or type-2 generalized beta distribution. This computationally efficient model accurately reproduces the published experimental polarization switching waveforms and the switching current waveforms in response to all reported applied voltage waveforms. The model tracks the polarization history so that it can simulate the transition between major and minor and among minor loops as well as accumulative polarization which cannot be captured by the conventional models. This model is intended for simulating circuits containing FE capacitors using commercial SPICE simulators for arbitrary applied voltage waveforms. It also has the capability of simulating the discrete switching and device variability in small-area FE capacitors having a small number of grains, although there is no available experimental data to check the model accuracy in this regard. [ABSTRACT FROM AUTHOR]

We present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for cryogenic IC applications such as quantum computing. For the core model charge density/surface potential calculation, we introduce an effective temperature formulation to capture the effects of the band tail states. We also present a compact model that corrects the low-temperature threshold voltage for the band-tail states, Fermi–Dirac statistics, and interface traps. New temperature-dependent mobility and velocity saturation models are accurate down to cryogenic temperature. In addition, we propose that experimentally observed ${I}_{D}$ dependence of subthreshold swing (SS) at cryogenic temperatures is a consequence of the expectedly higher rate of Coulomb scattering of free carriers. [ABSTRACT FROM AUTHOR]

Drain-extended MOSFET (DEMOS) with halo implant induced laterally asymmetric channel doping shows anomalous characteristics across bias and temperature that cannot be captured by existing models. The transconductance (gm) maxima in the linear region is found to be not only a function of the peak mobility but also the halo doping density. In the saturation region, the gm characteristics show a nonmonotonic “hump” induced by the halo-region/channel-region junction barrier. Another key care-about for analog design - the drain current (ID) mismatch, also exhibits unique characteristics with excess mismatch in the weak-inversion (WI) region, in particular at low temperature. In addition, the anomalous flicker noise (1/ƒ noise) trends in the presence of high-trap density in the halo region of halo-implanted DEMOS are also discussed. In this work, we propose an analytical model based on the equivalent conductance and impedance field theory to capture these effects. The proposed model is in good agreement with measurements and numerical device simulations using technology computer-aided design (TCAD) of DEMOS across a different oxide thickness, geometry, bias, and temperature. [ABSTRACT FROM AUTHOR]

In this brief, we present an improved model of bulk charge effect for both drain current (${I}_{\text {DS}}$) and capacitances and its implementation in the industry standard Berkeley short-channel IGFET model (BSIM)-BULK model. The proposed model captures all the well-known and important bulk charge effects, as the Abulk term does for BSIM3/BSIM4. The model is validated with the experimental and technology computer-aided design (TCAD) data. The proposed model enhances the fitting accuracy for ${I}_{\text {DS}}$ , and more importantly its derivatives and capacitances too. [ABSTRACT FROM AUTHOR]

A lumped-circuit nonquasi-static (NQS) model, that is applicable for both large-signal transient simulations and a small-signal ac analysis, is developed in this paper. An improved physical equivalent circuit, capturing NQS effects in the millimeter waveband, is derived using a transmission line model, by incorporating the high-frequency longitudinal gate electrode and a channel distributed RC network. The proposed model is implemented in a BSIM-BULK MOSFET model and validated with dc and RF data, obtained from technology computer-aided design device simulations and experimental data. The proposed model is in very good agreement with the data up to ${50}{f}_{t}$. The transient currents, for a gate-voltage switching rate of ${5}\times {10}^{{10}}$ V/s, show excellent match with the data. The dc, transient, and ac simulations using the proposed model are much faster than a 10-segmented MOSFET model. This shows that the proposed model is better than other computationally complex compact models, for most RF applications. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

In this paper, we report anomalous behavior of transconductance ( gm ) in halo implanted MOSFET for linear and saturation regions across both gate and body biases. The gm characteristics undergo sharp change of slope in saturation which cannot be modeled by conventional compact models. The cause of such behavior is identified and explained using the TCAD simulations of source side halo, drain side halo (DH), both side halos, and uniformly doped transistors. An analytical model, based on the equivalent conductance of the halo device, is developed to understand the gm behavior. It is shown that the commonly used approach where only the DH region is considered in saturation, is insufficient to model the atypical gm behavior. The effect of oxide thickness ( T\text {ox} ) variation on gm is also studied, which demonstrates a deviation from the conventional gm behavior for halo implanted devices with thicker T\text {ox} . A computationally efficient SPICE model is proposed to model gm characteristics which shows excellent matching with the measured data. [ABSTRACT FROM PUBLISHER]

In this letter, we present a unified compact model, which accurately captures carrier transport from the drift-diffusion to ballistic regime. This is a single unified model, which accounts for carrier degeneracy effects in ballistic transport. The model is implemented into the industry standard compact models for FinFETs, fully depleted silicon-on-insulator (FDSOI) devices and bulk MOSFETs: 1) Berkeley Spice model for common multi-gate; 2) Berkeley Spice model for independent multi-gate; and 3) BSIM6. The model is validated with experimental data and TCAD simulations for FDSOI devices, FinFETs, and bulk MOSFETs. [ABSTRACT FROM PUBLISHER]

We present a charge-based compact model for induced gate thermal noise for a fully depleted silicon-on-insulator transistor. The model uses front- and back-gate charges as well as the respective mobilities for the development of analytical expression. The model is implemented in Verilog-A and validated with experimentally calibrated TCAD simulations. The model predicts the high-frequency behavior with good accuracy while capturing the back-bias dependence. [ABSTRACT FROM AUTHOR]

We enhance the capability of industry standard compact model BSIM6 to model the parasitic current $ I_{{\text {edge}}}$ at the shallow trench isolation edge. Accurate, efficient, and scalable model for $ I_{{\text {edge}}}$ is developed by finding the key differences between $ I_{{\text {edge}}}$ and main device drain current ( $ I_{{\text {main}}}$ ). It is found that $ I_{{\text {edge}}}$ has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to $ I_{{\text {main}}}$ . These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage. [ABSTRACT FROM PUBLISHER]

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source–drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node. [ABSTRACT FROM PUBLISHER]

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX. [ABSTRACT FROM AUTHOR]