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This paper presents a generalized novel design of a family of multiplier free orthogonal wavelet filter banks (FBs) with low complexity. In the proposed method, maximum number of zeros at $z=-1$ is ensured for a desired length of analysis and synthesis filters. A new class of technique is proposed to obtain dyadic filter coefficients based on double shifting orthogonality property with allowable deviation from original filter coefficients. This is achieved by slightly altering perfect reconstruction (PR) condition to obtain dyadic filter coefficient. A general closed form expression is formulated using double shifting orthogonality property to reduce the error between original filter coefficients and proposed dyadic filter coefficients. The designed wavelet FB improved time-frequency product, Sobolev regularity and frequency selectivity (low energy in error) over well known existing wavelet FBs. In addition, a fixed point VLSI architecture is proposed for the designed family of orthogonal wavelet FBs. The suggested architecture is designed and implemented on Kintex7 FPGA board. The proposed family of orthogonal wavelet FBs is multiplier less with significantly reduced adders, shifters and dynamic power dissipation. The performance of the proposed wavelet FB is validated on two different applications namely image compression and medical image retrieval. The proposed FBs are tested on well known datasets such as CLASSIC, EPFL, RAISE, and FiveK for image compression and on three different medical image databases such as NEMA, OASIS, and EXACT09 for image retrieval. [ABSTRACT FROM AUTHOR]

This brief presents a novel VLSI architecture for computing discrete wavelet packet transform (DWPT) for the continuous flow of data. Each stage of the proposed multi-stage architecture consists of the bit-reordering circuit and serial wavelet filter. The conventional wavelet filter has been modified for single path serial data. The intermediate coefficients are reordered with the help of a bit reordering circuit in order to maintain a continuous flow of data from input to output end with minimum memory and minimum latency. In comparison to the recently published architectures, the proposed one not only reduces the memory requirement by more than 50% but also achieves a 100% hardware utilization ratio. Furthermore, the area and power requirements are reduced by more than 60% and 50%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a digital signal processing (DSP) architecture for real-time and distortion-free recovery of electrically-evoked compound action potentials (ECAPs) from stimulus artifacts and periodic noises in bidirectional neural response telemetry (NRT) system. In this DSP architecture, a low computation-cost bidirectional-filtered coherent averaging (BFCA) method is proposed for programmable linear-phase filtering of ECAPs, which can be easily combined with the alternating-polarity (AP) stimulation method to reject stimulus artifacts overlapped with ECAP responses. Design techniques including the configurable folded infinite-impulse response (IIR) filter and division-free averaging are also presented for efficient hardware implementation. Implemented in 180-nm CMOS process, the proposed DSP architecture consumes 10.03-mm2 area and 2.35-mW post-layout simulated power. The efficacy of the DSP architecture in recovering ECAPs from recorded neural data contaminated by overlapped stimulus artifacts and periodic noises is validated in in-vivo electrical nerve stimulations. Experiment results show that compared with the previous coherent averaging technique, the proposed DSP architecture improves the signal-to-noise ratio (SNR) of ECAP responses by 11 dB and achieves a 3.1% waveform distortion that is 17.1× lower. [ABSTRACT FROM AUTHOR]

Transform model estimation (TME) is a geometric operation, widely utilized in real-time imaging systems. Considering the massive computational load of matrix algebra-based TME realizations, most of the imaging systems resort to highly paralleled software-platform-based TME execution, which is power-intensive and expensive. Due to low-speed and power intensiveness, existing hardware for TME is not capable enough to meet the requirements of real-time systems. In this article, a hardware-realizable method of three-degree-of-freedom TME is formulated encompassing both the conventional CORDIC and the proposed modified CORDIC. The novelties of the proposed TME method and the corresponding architecture are that its latency sublinearly varies with the precision and the total computation time (CT) is almost independent of the input image sizes. The performance of prototype 16-bit fixed-point TME architecture (realized using VHDL in Xilinx Vivado 18.2) is compared with the software-counterpart. The proposed TME hardware is utilized along with other standard hardware modules to realize image registration (IR) operation. The proposed IR architecture achieves, on average, 60% reduction in total CT, $1.61 \times $ increase in maximum operating frequency with a comparable accuracy, only at the cost of 23% increase in power consumption with respect to other existing IR hardware. [ABSTRACT FROM AUTHOR]

This article proposes an encoding method based on a two-step encoding algorithm for the 12 quasi-cyclic (QC)-low-density parity-check (LDPC) (QC-LDPC) codes specified in the IEEE 802.11n/ac/ax standards. The proposed approach jointly considers all codes of the particular set, instead of targeting each code separately. The proposed algorithm performs multiplication by inverse matrices. The complexity of the multiplications is significantly reduced by the introduced encoding method. It allows the implementation of full-parallel architectures that execute the encoding process within a single clock cycle, or more for pipelined implementations, for any of the supported codes. A corresponding VLSI encoding architecture based on XOR-gate trees is also proposed. The proposed solution exploits the structure and features of the involved matrices to extract common subexpressions (CSs) using common sub-expression sharing techniques (CSST). Such expressions result due to common features of the original matrices and the corresponding inverses, identified in this article. Innovative subexpression extraction procedures that target the specific codes as a set are introduced here. Furthermore, illustrative single-clock hardware encoders derived by the proposed technique are integrated into 90- and 45-nm technologies at 1 GHz occupying 125 and 107 KGates, respectively, achieving throughput rates up to 1.62 Tbps. [ABSTRACT FROM AUTHOR]

In this brief, we propose a low complexity VLSI architecture design Methodology for Wigner Ville Distribution (WVD) computation. The proposed methodology performs both auto and cross WVD computations using only the half number of Fast Fourier transform (FFT) computations as opposed to the state of the art methodologies. The FPGA implementation for proposed methodology was performed for 16 bit fixed point and 32 bit single precision floating point numbers on the Xilinx Virtex-7 FPGA (XC7vx485tffg). The proposed methodology saves 49% energy consumption when compared with the state of the art methodology. However it can be noted that the proposed methodology is independent of the VLSI implementation platform and technology node. [ABSTRACT FROM AUTHOR]

To enable the continued scaling of distributed storage, failure recovery schemes that have low latency and low redundancy are indispensable. Minimum storage regenerating (MSR) codes have been developed to achieve this goal. Compared to other MSR codes, the recent coupled-layered (Clay) codes have many advantages such as low sub-packetization level, small finite field for construction, and uniform repair bandwidth over data and parities. This brief proposes efficient VLSI architectures for Clay encoder and decoder. Through exploiting subfield elements of finite fields, the logic complexity is substantially lowered. Additionally, the buffer size is reduced by optimizing the coupling scheme. For an example Clay code with (n,k)=(6,4), the proposed designs achieve 12% and 24% logic complexity reduction on the encoder and decoder, respectively, under the same timing constraint. [ABSTRACT FROM AUTHOR]

This article presents a piecewise linear approximation computation (PLAC) method for all nonlinear unary functions, which is an enhanced universal and error-flattened piecewise linear (PWL) approximation approach. Compared with the previous methods, PLAC features two main parts, an optimized segmenter to seek the minimum number of segments under the predefined software maximum absolute error (MAE), raising the segmentation performance to the highest theoretical level for logarithm, and a novel quantizer to completely simulate the hardware behavior and determine the required bit width and ${\text {MAE}}_{c}$ (MAE in circuits) for hardware implementation. In addition, the hardware architecture is also improved by simplifying the indexing logic, leading to nonredundant hardware overhead. The ASIC implementation results reveal that the proposed PLAC can improve all metrics without any compromise. Compared with the state-of-the-art methods, when computing logarithmic function, PLAC reduces 2.80% area, 3.77% power consumption, and 1.83% ${\text {MAE}}_{c}$ with the same delay; when approximating hyperbolic tangent function, PLAC reduces 6.25% area, 4.31% power consumption, and 18.86% ${\text {MAE}}_{c}$ with the same delay; when evaluating sigmoid function, PLAC reduces 16.50% area, 4.78% power consumption with the same delay, and ${\text {MAE}}_{c}$ ; and when calculating softsign function, PLAC reduces 17.28% area, 11.34% power consumption, 12.50% delay, and 33.28% ${\text {MAE}}_{c}$. [ABSTRACT FROM AUTHOR]

The metric-first-based multiple-input–multiple-output (MIMO) detection algorithm can achieve optimal performance with large stack size, which leads to huge memory consumption and extremely high-sorting complexity. This article presents the algorithm and architecture of a soft-input–soft-output metric-first MIMO detection. The proposed algorithm divides the global stack into multiple local stacks for each nonleaf of the tree. Furthermore, each level of the search tree is performed in parallel to improve the throughput and hardware efficiency. In the proposed algorithm, the hybrid enumeration strategy significantly reduces the computational complexity by avoiding the full enumeration and sorting. The simulation results show the novel algorithm can achieve good performance with lower complexity than other metric-first methods. The proposed detector has been designed for a $4\times 4\,\,64$ -QAM MIMO system and implemented in SMIC 65-nm CMOS technology. The detector can operate at 333-MHz clock frequency and achieve a maximum throughput of 799.2 Mb/s at a 17.3-dB signal-to-noise ratio with area equivalent 242 kg and power consumption of 102.3 mW, and the hardware efficiency is 3.3 Mb/s/kg. Compared with other detectors based on the metric-first algorithm, this article has an obvious advantage in terms of throughput and hardware efficiency. [ABSTRACT FROM AUTHOR]

A novel high-efficient reconstruction architecture of compressed sensing and an area-efficient integrated source-channel decoder based on Reed-Solomon (RS) code are proposed in this letter. The proposed reconstruction architecture only includes a parameter calculation (PC) block and a target locator and evaluator solution (TLES) block, resulting in 30 times higher throughput rate achieved and 85% area saved compared with previously reported reconstruction architecture based on orthogonal marching pursuit (OMP) algorithm. Moreover, the proposed integrated source-channel decoder can reduce 15.3% and 28.5% area respectively for the sampling rate of 25% and 12.5%. [ABSTRACT FROM AUTHOR]

This paper proposes an area-efficient fixed-point architecture for the computation of the discrete cosine transform (DCT) of multiple sizes in high efficiency video coding (HEVC). This result is obtained by comparing different DCT factorizations in order to find the most suitable one for implementation in the HEVC encoder. The recursive structure of fast algorithms, which decompose the $N$ -point DCT by means of two $N/2$ -point DCTs, is exploited to execute computations of small-size DCTs in parallel, thus maximizing the hardware re-usability while maintaining a constant throughput. The simulation results prove that the proposed solution features reduced rate-distortion loss es, with relevant complexity saving compared with the state-of-the-art implementations. Finally, the proposed architecture is exploited to design two families of architectures for the 2D-DCT, namely, folded and full-parallel. [ABSTRACT FROM AUTHOR]

This brief proposes a new selective-sampling technique that enables spectrum sensing of orthogonal-frequency division multiplexing primary users with 64, 128, 256, 512, and 1024 subcarriers for contemporary cognitive-radio wireless networks. Reconfigurable and memory-efficient very-large scale-integration architecture of the time-domain cyclostationary detector, based on this new technique, has been designed for spectrum sensing. In addition, we present robust coordinate rotation digital-computer architecture for our detector that reduces the computational error to achieve adequate performance. Our detector is post-layout simulated in 90-nm CMOS process and field-programmable gate array implemented that processes the real-world signals captured using universal-software radio peripheral transceivers. In comparison with the state-of-the-art technique, this design alleviated memory requirement by 99% and other hardware resources by 33%. [ABSTRACT FROM AUTHOR]

Quasi-cyclic low-density parity-check (QC-LDPC) codes are adopted in many digital communication and storage systems. The encoding of these codes is traditionally done by multiplying the message vector with a generator matrix consisting of dense circulant submatrices. To reduce the encoder complexity, this paper introduces two schemes making use of finite Fourier transform. We focus on QC-LDPC codes whose circulant submatrices are of dimension (2^r-1)\times (2^r-1) and the entries are elements of GF (2^p) , where p divides r , and hence, GF (2^p) is a subfield of GF (2^r) . These cover a broad range of codes, and binary LDPC codes are a special case. Making use of conjugacy constraints, low-complexity architectures are developed for finite Fourier and inverse transforms over subfields in this paper. In addition, composite field arithmetic is exploited to eliminate the computations associated with message mapping and reduce the complexity of Fourier transform. For a (2016, 1074) nonbinary QC-LDPC code whose generator matrix consists of circulants of dimension 63 \times 63 with GF (2^2) entries, the proposed encoders achieve 22% area reduction compared with the conventional encoders without sacrificing the throughput. [ABSTRACT FROM PUBLISHER]

Improved video coding techniques introduced in the H.265/High Efficiency Video Coding (HEVC) standard allow video encoders to achieve better compression efficiencies. On the other hand, the increased complexity requires a new design methodology able to face challenges associated with ever higher spatiotemporal resolutions. This paper presents a computationally scalable algorithm and its hardware architecture able to support intra encoding up to 2160p@30 frames/s resolution. The scalability allows a tradeoff between the throughput and the compression efficiency. In particular, the encoder is able to check a variable number of candidate modes. The rate estimation based on bin counting and the distortion estimation in the transform domain simplify the rate–distortion analysis and enable the evaluation of a great number of candidate intra modes. The encoder preselects candidate modes by the processing of $8\times 8$ predictions computed from original samples. The preselection shares hardware resources used for the processing of predictions generated from reconstructed samples. To support intra $4\times 4$ modes for the 2160p@30 frames/s resolution, the encoder incorporates a separate reconstruction loop. The processing of blocks with different sizes is interleaved to compensate for the delay of reconstruction loops. Implementation results show that the encoder utilizes 1086k gates and 52-kB on-chip memories for TSMC 90 nm. The main reconstruction loop can operate at 400 MHz, whereas the remaining modules work at 200 MHz. For 2160p@30 frames/s videos, the average BD-rate is 5.46% compared with that of the HM software. [ABSTRACT FROM PUBLISHER]

Scaling is a key important arithmetic operation and is difficult to perform in Residue Number Systems (RNS). This paper proposes a comprehensive approach for designing efficient and accurate 2^n RNS scalers for important classes of moduli sets that have large dynamic ranges. These classes include the traditional 3-moduli set, but the exponent of the power of two modulo is augmented by a variable value x ( \lbrace 2^n-1, 2^n\underline+x, 2^n+1 \rbrace ), and any extended set with an additional modulo m_4 ( \lbrace 2^n-1, 2^n\underline+x, 2^n+1[,\underlinem_4]\rbrace ). The proposed approach embeds scaling into the formulation of the Chinese remainder theorem and the mixed radix system, and it exploits the properties of the target moduli sets to perform scaling explicitly in the RNS domain. This is accomplished by operating hierarchically on each channel without requiring reverse and forward conversions. Simple memoryless VLSI architectures are proposed based on the obtained formulations. The relative assessment indicates that not only are these architectures comprehensive and suitable for configurable systems, but they are also more efficient than the related state of the art in terms of both performance and energy. The experimental results obtained for a 90 nm CMOS ASIC technology show improvements in the area-delay product, normalized with respect to the dynamic range, of up to $57$ and $146$ percent with the proposed scalers for the augmented 3-moduli set (dynamic range of $4n-1$ bits) and an extended 4-moduli set (dynamic range of $6n$ bits), respectively. These improvements increase to $64.9$ and $263$ percent when the energy required per scaling is measured. The proposed scalers are not only flexible and cost-effective, but they are also suitable for designing and implementing energy-constrained devices, particularly mobile systems. [ABSTRACT FROM PUBLISHER]

A new resource efficient FPGA-based hardware architecture for real-time edge detection using Sobel operator for video surveillance applications has been proposed. The choice of Sobel operator is due to its property to counteract the noise sensitivity of the simple gradient operator. FPGA is chosen for this implementation due to its flexibility to provide the possibility to perform algorithmic changes in later stage of the system development and its capability to provide real-time performance, hard to achieve with general purpose processor or digital signal processor, while limiting the extensive design work, time and cost required for application specific integrated circuit. The proposed architecture uses single processing element for both horizontal and vertical gradient computation for Sobel operator and utilised approximately 38% less FPGA resources as compared to standard Sobel edge detection architecture while maintaining real-time frame rates for high definition videos (1920 × 1080 image sizes). The complete system is implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA board. [ABSTRACT FROM AUTHOR]

In this brief, we propose a high-throughput layered decoder architecture to support a broader family of quasicyclic low-density parity-check (QC-LDPC) codes, whose parity-check matrices are constructed from arrays of circulant submatrices. Each nonzero circulant submatrix is a superposition of K cyclic-shifted identity matrices, where the circulant weight K\geq 1. We propose a novel layered decoder architecture to support QC-LDPC codes with any circulant weight. We present a block-serial decoding architecture which processes a layer of a parity check matrix block by block, where each block is a Z\times Z circulant matrix with a circulant weight of K. In the case study, we demonstrate an LDPC decoder design for the China Mobile Multimedia Broadcasting (CMMB) standard, which was synthesized for a TSMC 65-nm CMOS technology. With a core area of 3.9 mm^2, the CMMB LDPC decoder achieves a maximum throughput of 1.1 Gb/s with 15 iterations. [ABSTRACT FROM PUBLISHER]

This paper proposes a data bandwidth-oriented motion estimation design for resource-limited mobile video applications using an integrated bandwidth rate distortion optimization framework. This framework predicts and allocates the appropriate data bandwidth for motion estimation under a limited bandwidth supply to fit a dynamically changing bandwidth supply. The simulation results show that our proposed algorithm can achieve 66% and 41% memory bandwidth savings while maintaining an equivalent rate-distortion performance and meeting real-time targets, when compared with conventional approaches for low-motion and high-motion D1 (704\,\times\,576)-size video, respectively. The final implementation costs 122 K gate counts with TSMC 0.13-\mum CMOS technology and consumes 74 mW of power for D1 resolution at 30 frames/s which is 40% of that achieved in previous designs. [ABSTRACT FROM AUTHOR]

Abstract: The embedded block coding with optimized truncation (EBCOT) algorithm is the heart of the JPEG 2000 image compression system. The MQ coder used in this algorithm restricts throughput of the EBCOT because there is very high correlation among all procedures to be performed in it. To overcome this obstacle, a high throughput MQ coder architecture is presented in this paper. To accomplish this, we have studied the number of rotations performed and the rate of byte emission in an image. This study reveals that in an image, on an average 75.03% and 22.72% of time one and two shifts occur, respectively. Similarly, about 5.5% of time two bytes are emitted concurrently. Based on these facts, a new MQ coder architecture is proposed which is capable of consuming one symbol per clock cycle. The throughput of this coder is improved by operating the renormalization and byte out stages concurrently. To reduce the hardware cost, synchronous shifters are used instead of hard shifters. The proposed architecture is implemented on Stratix FPGA and is capable of operating at 145.9MHz. Memory requirement of the proposed architecture is reduced by a minimum of 66% compared to those of the other existing architectures. Relative figure of merit is computed to compare the overall efficiency of all architectures which show that the proposed architecture provides good balance between the throughput and hardware cost. [Copyright &y& Elsevier]

H.264/AVC intra-frame encoding contains several computation-intensive coding tools that form a long data dependency loop that is difficult to speed up. In this paper, we present a low-power and high-performance H.264/AVC intra-frame encoder. We propose several novel approaches to alleviate the performance bottleneck caused by the long data dependency loop among 4\,\times\,4 luma blocks, integrate an efficient CABAC entropy encoder, and apply a clock-gating technique to reduce power consumption. Synthesized into a TSMC 0.13 \mum CMOS cell library, our design requires 265.3 K gates at 114 MHz and consumes 23.56 mW to encode 1080pHD (1920\,\times\,1088) video sequences at 30 frames per second (fps). It also delivers the same video quality as the H.264/AVC reference software. Compared with all state-of-the-art designs, our design has a lower working frequency and achieves both better bit-rate saving and lower power consumption. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a practically realisable VLSI architecture for a 4×4 16-QAM MIMO wireless communication system using the Vertical Bell Labs Layered Space-Time (V-BLAST) detection scheme. The proposed implementation employs the QR-factorisation technique. The design and optimisation of the pre-decoder block are carried out using the COordinate Rotation DIgital Computer (CORDIC) processors. In order to avoid the numerical problems associated with Back Substitution (BS) based Symbol Interference Cancellation (SIC), a modified BS-SIC architecture that eliminates the need for division and multiplication is proposed. Not only does this substantially reduce the hardware cost, but also enjoys improved numerical stability. As the decoder hardware design can also be simplified by rendering it oblivious to the power normalisation in the transmitter side of the MIMO wireless system, we have designed a matching compensation unit at the receiver. The resulting VLSI architecture was implemented on an Altera Stratix Field Programmable Gate Array (FPGA) platform and on a 0.18μm Application Specific Integrated Circuits (ASIC) platform. Detection throughput ratings of 149Mbps and 212Mbps were achieved. However, the lower hardware complexity of the BS-SIC based decoder architecture comes at the cost of a degradation in the Bit Error Rate (BER) performance with respect to the original higher complexity V-BLAST. Therefore, we also propose a novel parallel decoding scheme that is aimed at improving the system BER. This novel scheme allows for a compromise between the hardware overhead and the BER performance. As the hardware complexity is increased, the performance approaches the original V-BLAST limit. [Copyright &y& Elsevier]

Image pipeline processing is crucial to generating high quality images in applications using complementary metal-oxide-semiconductor (CMOS)/charge-coupled device sensors. The on-chip line buffer normally dominates the total area and power dissipation due to the needed filter window buffering. As image resolution and filter support increase, the area and power requirement increase accordingly. This paper presents a novel pyramid architecture to efficiently process a system that the image pipeline is between an image sensor and video coding engine. By utilizing the features of the pyramid structure and block-based video/image encoders, the proposed architecture is scalable from low to high image resolution and filter size. The input image is first partitioned into floors of tiles to reduce the frame line buffer. Two computing schemes, immediate result reuse and vertical snack scan, are utilized to reduce the overlapping redundant computations. A 90 nm CMOS chip design with 7\,\times\,5 filter support for 3840\,\times\,2160 quad full high definition video at 30 frames/s is designed to demonstrate the performance of power and area efficiency. Compared with traditional architectures with frame line buffers, the proposed design has shown that the power consumption is reduced by 25% to 108 mW from 145 mW. The chip area is reduced by 65% to 309 K from 888 K logic gates. The external memory bandwidth increases to 8286 Mbit/s from 5972 Mbit/s for YUV4:2:0, from 7963 Mbit/s for YUV4:2:2, and is reduced by 30% from 11944 Mbit/s for YUV4:4:4. [ABSTRACT FROM PUBLISHER]

This paper presents an architecture of the lifting based running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3-DDWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput compared to those of earlier reported works. The proposed architecture has been successfully implemented on Xilinx Virtex-IV series field-programmable gate array, offering a speed of 321 MHz, making it suitable for realtime compression even with large frame dimensions. Moreover, the architecture is fully scalable beyond the present coherent Daubechies filterbank (9, 7). [ABSTRACT FROM AUTHOR]

Variable block-size motion estimation (VBSME) has become an important technique in H.264/A VC to improve video quality. In this paper, we propose a scalable VLSI architecture for VBSME in H.264/A VC based on a full-search motion estimation algorithm. A new scan order is introduced to re-use the sum of absolute differences (SAD) values of smaller sub-blocks on an "as-early-as-possible" basis, thus the complexity of the required hardware resources, such as registers, multiplexers, and controls is reduced. It also spreads the timing for the final SAD outputs so that the number of output buses is reduced. The architecture is flexible and scalable with regard to the size of the searching windows and PE arrays. Compared to the conventional approaches, the architecture shows higher throughput rate with less hardware. After logic synthesis using DongbuAnam 0.18 μm standard cell library, the number of gates is 39K (16 PEs) in two-input equivalent NAND gates and the maximum operating clock frequency is 416 MHz (256 fps@CIF). [ABSTRACT FROM AUTHOR]

This paper presents an efficient architecture of an application specific processor (ASP) designed for the deblocking filter algorithm of the H.264 video compression standard. Several optimization techniques at different design levels, such as vector register, pipeline processing, very long instruction word (VLIW) processor, and predication, are utilized in this design. The proposed ASP can meet the real timeconstraint of the deblocking filter algorithm for the 16:9 video format (4690 x 2304) at 30 frames per second (fps) at 200-MHz clock rate. [ABSTRACT FROM AUTHOR]

Modular exponentiation with a large modulus, which is usually accomplished by repeated modular multiplications, has been widely used in public key cryptosystems for secured data communications. To speed up the computation, the Montgomery modular multiplication algorithm is used to relax the process of quotient determination, and the carry-save addition (CSA) is employed to reduce the critical path delay. In this paper, based on the inherent data dependency between the modular multiplication and square operations in the H-algorithm of modular exponentiation, we present a new modular exponentiation architecture with a unified modular multiplication/square module and show how to reduce the number of input operands for the CSA tree by mathematical manipulation. The developed architecture has the following advantages. 1) There is no need to convert the carry-save form of an operand into its binary representation at the end of each modular multiplication. In this way, except the final step to get the result of modular exponentiation, the time-consuming carry propagation can then be eliminated. 2) The number of input operands for the CSA tree is reduced in a very efficient way. 3) The hardware saving is achieved with very limited impact on the original critical path delay when designed with two distinct modular multiplication and square components. Experimental results show that our modular exponentiation design obtains the least hardware complexity compared with the existing work and outperforms them in terms of area-time (AT) complexity as well. [ABSTRACT FROM AUTHOR]

Image registration is an ubiquitous task occurring in countless image analysis applications. A dedicated implementation of image registration algorithms is the best approach to meet the intensive computation requirements of implementing image registration schemes in real time. This paper presents an efficient VLSI architecture for real-time implementation of image registration algorithms using an exhaustive search method. Normalized cross correlation function, mean square error, and blue screen technique algorithms are implemented for image registration. The architecture is based on a data flow design that allows sequential inputs but performs parallel processing. Based on the architecture, a programmable chip can be designed for image registration. Chips can be cascaded to achieve better performance and sizes of both the search and the reference image which can vary with time from a small to a very large value. [ABSTRACT FROM AUTHOR]

Reed-Solomon (RS) codes are one of the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to hard-decision decoding, soft-decision decoding offers considerably higher error-correcting capability. The Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain, while maintaining a complexity polynomial with respect to the code word length. In the KV algorithm, the interpolation step dominates the decoding complexity. A reduced complexity interpolation architecture is proposed in this paper by eliminating the polynomial updating corresponding to zero discrepancy coefficients in this step. Using this architecture, an area reduction of 27% can be achieved over prior efforts for the interpolation step of a typical (255, 239) RS code, while the interpolation latency remains the same. [ABSTRACT FROM AUTHOR]

This paper presents an asynchronous VLSI architecture for modeling the oscillatory patterns seen in segmented biological systems. The architecture emulates the intersegmental synaptic connectivity observed in these biological systems. The communications network uses address-event representation (AER), a common neuromorphic protocol for data transmission. The asynchronous circuits are synthesized using communicating hardware processes (CHP) procedures. The architecture is scalable, supports multichip communication, and operates independent of the type of silicon neuron (spiking or burst envelopes). A 16-segment prototype system was developed, tested, and implemented; data from this system are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a novel flexible VLSI architecture for the implementation of variable block size motion estimation (VBSME). The architecture is able to perform a full motion search on integral multiples of 4 × 4 blocks sizes. To use the architecture, each 16×16 macroblock of the source frames should be partitioned into sixteen 4 × 4 non-overlapping subblocks, called primitive subblocks. The architecture contains sixteen modules and one VBSME processor. Each module, realized by cascading ID systolic arrays, is responsible for the block-matching operations of a different primitive subblock. The realization has the advantages of high throughput, high flexibility and 100 % processing element (PE) utilization. The motion estimation of all the primitive subblocks are performed in parallel. Because these primitive subblocks can be used to form the 41 subblocks of different sizes specified by the H.264, the VBSME processor is employed to concurrently compute the sums of absolute differences (SADs) of all the 41 subblocks from the SADs of the primitive subblocks. This new architecture has lower latency and higher throughput over other exiting VBSME architectures for the hardware implementation of H.264 encoders. [ABSTRACT FROM AUTHOR]

Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent 5150 outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times Sd throughput for large blocks is increased up to six-fold relative to, sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area. [ABSTRACT FROM AUTHOR]

Reed-Solomon (RS) codes are among the most widely utilized block error-correcting codes in modem communication and computer systems. Compared to its hard-decision counterpart, soft-decision decoding offers considerably higher error-correcting capability. The recent development of soft-decision RS decoding algorithms makes their hardware implementations feasible. Among these algorithms, the Koetter.-Vardy (KV) algorithm can achieve substantial coding gain for high-rate RS codes, while maintaining a polynomial complexity with respeét to the code length. In the KY algorithm, the factorization step can consume a major part of the decoding latency. A novel architecture based on root-order prediction is proposed in this paper to speed up the factorization step. As a result, the time-consuming exhaustive-search-based root computation in each iteration level, except the first one, of the factorization step is circumvented with more than 99% probability. Using the proposed architecture, a speedup of 141 % can be achieved over prior efforts for a (255,239) RS code, while the area consumption is reduced to 31.4%. [ABSTRACT FROM AUTHOR]

Currently, considerable research is being performed on multiplierless structural methods for fixed coefficient filters, but not much research has been done on structural methods for creating adaptive filters whose coefficients vary with time. A few multiplierless structural methods have been proposed as structural methods using distributed arithmetic, but these conventional methods use particular encoding for input signals, and thus experience very high levels of degradation in their convergence characteristics. The authors improve significantly the convergence characteristics by generalizing this method using a new two's complement method. In addition, the authors propose a VLSI architecture not considered in conventional methods and perform VLSI evaluations of their structural method. The results show that the authors' proposed method can dramatically reduce power consumption and hardware requirements while sustaining high performance and very low latency compared to structural methods that use a multiplier. © 2001 Scripta Technica, Electron Comm Jpn Pt 3, 84(5): 1–12, 2001 [ABSTRACT FROM AUTHOR]