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We define a new algebraic form for Boolean function representation, called EXOR-Projected Sum of Products(EP-SOP), consisting in a four level network that can be easily implemented in practice. Deriving an optimal EP-SOP from an optimal SOP form is a NPNP-hard problem; nevertheless we propose a very efficient approximation algorithm, which returns, in polynomial time, an EP-SOP form whose cost is guaranteed to be near the optimum. Experimental evidence shows that for about 35% of the classical synthesis benchmarks, EP-SOP networks have a smaller area and delay with respect to the optimal SOPs (sometimes gaining even 40-50% of the area). Since the computational times required are extremely short, we recommend the use of the proposed approach as a post-processing step after SOP minimization. [ABSTRACT FROM AUTHOR]

This paper gives an overview of results of the Human++ research program [1]. This research aims to achieve highly miniaturized and nearly autonomous sensor systems that assist our health and comfort. It combines expertise in wireless ultra-low power communications, packaging and 3D integration technologies, MEMS energy scavenging techniques and low-power design techniques. Key words. BAN, microsystem, wireless, autonomous, integration [ABSTRACT FROM AUTHOR]

In recent years, dynamic reconfigurable processor which can achieve reconfiguration with a few cycles is proposed. The fast recon- figuration makes run-time reconfiguration possible, and the run-time reconfiguration gives a new possibility to the dynamic reconfigurable processor, i.e. the dynamic reconfigurable processor can also execute partitioned independent subtasks with repeated reconfigurations and executions. However, to achieve an execution with the run-time reconfiguration, performance should be evaluated with various overheads: reconfiguration, memory accesses, etc. The overheads depend on reconfigurable architectures, and it is generally difficult to evaluate the overhead. As the overhead may critically affect the performance, designers should carefully explore design space for suitable architectures. In this paper, we propose a dynamic reconfigurable architecture exploration method based on Parameterized Reconfigurable Processor model (PRP-model) and task partitioning optimization algorithm for architecture exploration corresponding to proposed PRP-model. Experimental results showed that the proposed PRP-model and the task partitioning algorithm for PRP-model can fast evaluate various reconfigurable architectures, and designers can easily find suitable reconfigurable architectures by changing the PRPmodel parameters. [ABSTRACT FROM AUTHOR]

The growing complexity of multiprocessor systems on chip make the integration of Intellectual Property (IP) blocks into a working system a major challenge. Networks-on-Chip (NoCs) facilitate a modular design approach which addresses the hardware challenges in designing such a system. Guaranteed communication services, offered by the Æthereal NoC, address the software challenges by making the system more robust and easier to design. This paper describes two existing bus-based reference designs and compares the original interconnects with an Æthereal NoC. We show through these two case study implementations that the area cost of the NoC, which is dominated by the number of network connections, is competitive with traditional interconnects. Furthermore, we show that the latency in the NoC-based design is still acceptable for our application. [ABSTRACT FROM AUTHOR]

This paper presents a method of broadside transition test generation for partial scan circuits. The proposed method first transforms the kernel circuit of a given partial scan circuit into some combinational circuits. Then, by performing stuck-at test generation on the transformed circuits, broadside transition tests for the original circuit are obtained. This method allows us to use existing stuck-at test generation tools in order to generate broadside transition tests. It is shown that the proposed scheme is effective in area overhead and test generation time by experiments. In this paper, some variations of broadside transition testing of partial scan circuits are also discussed in terms of different test application strategies and fault sizes. [ABSTRACT FROM AUTHOR]

This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence Design Framework Environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that accounts for process deviations, as a trade-off between estimated test metrics at the design stage. Specification-based tests are next optimized in terms of their capability of detecting catastrophic and parametric faults. [ABSTRACT FROM AUTHOR]

This paper presents an algorithm for I/O pins partitioning and placement targeting 3D circuits. The method starts from a standard 2D placement of the pins around a flat rectangle and outputs a 3D representation of the circuit composed of a set of tiers and pins placed at the four sides of the resulting cube. The proposed algorithm targets a balanced distribution of the I/Os that is required both for accommodating the pins evenly as well as to serve as an starting point for cell placement algorithms that are initially guided by I/O's locations, such as analytical placers. Moreover, the I/O partitioning tries to set pins in such a way the it allows the cell placer to reach a reduced number of 3D-Vias. The method works in two phases: first the I/O partitioning considering the logic distances as weights; second, fix the I/Os and perform partitioning of the cells. The experimental results show the effectiveness of the approach on balance and number of 3D-Vias compared to simplistic methods for I/O partitioning, including traditional min-cut algorithms. Since our method contains the information of the whole circuit compressed in a small graph, it could actually improve the partitioning algorithm at the expense of more CPU time. Additional experiments demonstrated that the method could be adapted to further reduce the number of 3D-Vias if the I/O pin balance constraint can be relaxed. [ABSTRACT FROM AUTHOR]

Networks on Chip(NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can lead to deadlock-free operation with minimum power and area overhead are important for designing application-specific NoCs. The deadlocks that can occur in NoCs can be broadly categorized into two classes: routingdependentdeadlocks and message-dependentdeadlocks. In this work, we present methods to design NoCs that avoid both types of deadlocks. The methods are integrated with the topology synthesis phase of the NoC design flow. We show that by considering the deadlock avoidance issue during topology synthesis, we can obtain a significantly better NoC design than traditional methods, where the deadlock avoidance issue is dealt with separately. Our experiments on several SoC benchmarks show that our proposed scheme provides large reduction in NoC power consumption (an average of 38.5%) and NoC area (an average of 30.7%) when compared to traditional approaches. Keywords: Networks on Chips, Systems on Chips, Message-dependent deadlocks, routing-dependent deadlocks, topology, synthesis. [ABSTRACT FROM AUTHOR]

This work presents the design of an on-line energy optimizer unit, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements (PE), tailored to the instantaneous workload information and is fully adaptive to variations in process and temperature. The circuit design borrows some of the basic principles of analog computation to continuously optimize the system-wide energy dissipation of multiple cores. The analogy between the energy minimization problem under timing constraints in a general task graph and the power minimization problem under Kirchhoff's current law (KCL) constraints in an equivalent resistive network is exploited. To our best knowledge, this is the first study of its kind to demonstrate an on-line solution to complex, multi-variable energy optimization problem which allows dynamic adjustment of individual operating frequencies and supply voltages of multiple processing elements. [ABSTRACT FROM AUTHOR]

Autonomous mobile robots have been achieving significant improvement in recent years. Intelligent mobile robots may detect hazardous materials or survivors after a disaster. Mobile robots usually carry limited energy (mostly rechargeable batteries) so energy conservation is crucial. In a mobile robot, the processor and the motors are two major energy consumers. While a robot is moving, it has to detect an obstacle before a collision. This results in a real-time constraint: the processor has to distinguish an obstacle within the traveled time interval. This constraint requires that the processor run at a high frequency. Alternatively, the robot's motors can slow down to enlarge the time interval. This paper presents a new approach to simultaneously adjust the processor's frequency and the motors' speed to conserve energy and meet the real-time constraint. We formulate the problem as non-linear optimization and solve the problem using a genetic algorithm for both continuous and discrete cost functions. Our experiments demonstrate that more energy can be saved by adjusting both the frequency and the speed simultaneously. [ABSTRACT FROM AUTHOR]

This work introduces an application mapping methodology and case study for multi-processor on-chip architectures. Starting from the description of an application in standard sequential code (e.g. in C), first the application is pro- filed, parallelized when possible, then its components are moved to hardware implementation when necessary to satisfy performance and power constraints. After mapping, with the use of hardware objects to handle concurrency, the application power consumption can be further optimized by a task-based scheduler for the remaining software part, without the need for operating system support. The key contributions of this work are: a methodology for high-level hardware/software partitioning that allows the designer to use the same code for both hardware and software models for simulation, providing nevertheless preliminary estimations for timing and power consumption; and a task-based scheduling algorithm that does not require operating system support. The methodology has been applied to the co-exploration of an industrial case study: an MPEG4 VGA real-time encoder. [ABSTRACT FROM AUTHOR]

With technology steadily progressing into nanometer dimensions, precise control over all aspects of the fabrication process becomes an area of increasing concern. Process variations have immediate impact on circuit performance and behavior and standard design and signoff methodologies have to account for such variability. In this context, timing verification, already a challenging task due to the sheer complexity of todays designs, becomes an increasingly difficult problem. Statistical static timing analysis has been proposed as a solution to this problem, but most of the work has focused in the development of timing engines for computing delay propagation. Such tools rely on the availability of delay formulas accounting for both cell and interconnect delay that take into account unpredictable variability effects. In this paper, we concentrate on the impact of interconnect on delay and propose an extension to the standard modeling strategies that is variation-aware and compatible with such statistical engines. Our approach, based on a specific type of perturbation analysis, allows for the analytical computation of the quantities needed for statistical delay propagation. We also show how perturbation analysis can be performed when only the standard delay table lookup models are available for the standard cells. This makes the proposed approach compatible with existing timing analysis frameworks. Results from applying our proposed modeling strategy to computing delays and slews in several instances accurately match similar results obtained using electrical level simulation. [ABSTRACT FROM AUTHOR]

This paper presents an overview of the Built-In Soft Error Resilience (BISER) technique for correcting soft errors in latches, flip-flops and combinational logic. The BISER technique enables more than an order of magnitude reduction in chip-level soft error rate with minimal area impact, 7-11% chip-level power impact, and 1-5% performance impact (depending on whether combinational logic error correction is implemented or not). In comparison, several classical error-detection techniques introduce 40-100% power, performance and area overheads, and require significant efforts in designing and validating corresponding recovery mechanisms. Design trade-offs associated with the BISER technique and other existing soft error protection techniques are also analyzed. [ABSTRACT FROM AUTHOR]

Technology scaling has traditionally offered advantages to embedded systems in terms of reduced energy consumption and die cost as well as increased performance, without requiring significant additional design effort. Scaling past the 45 nm technology node, however, brings a number of problems whose impact on system level design has not been evaluated yet. Random intra-die process variability, reliability degradation mechanisms and their combined impact on the system level parametric quality metrics are prominent issues that will need to be tackled in the next few years. Dealing with these new challenges will require a paradigm shift in the system level design phase. [ABSTRACT FROM AUTHOR]

Highly scaled CMOS devices in the nanoscale regime would inevitably exhibit statistical or probabilistic behavior. Such behavior is caused by process variations, and other perturbations such as noise. Current circuit design methodologies, which depend on the existence of "deterministic" devices that behave consistently in temporal and spatial contexts do not admit considerations for probabilistic behavior. Admittedly, power or energy consumption as well as the associated heat dissipation are proving to be impediments to the continued scaling (down) of device sizes. To help overcome these challenges, we have characterized CMOS devices with probabilistic behavior (probabilistic CMOS or PCMOS devices) at several levels: from foundational principles to analytical modeling, simulation, fabrication, measurement as well as exploration of innovative approaches towards harnessing them through system-on-a-chip architectures. We have shown that such architectures can implement a wide range of probabilistic and cognitive applications. All of these architectures yield significant energy savings by trading probability with which the device operates correctly—lower the probability of correctness, the greater the energy savings. In addition to these PCMOS based innovations, we will also survey probabilistic arithmetic—a novel framework through which traditional computing units such as adders and multipliers can be deliberately designed to be erroneous, while being characterized by a well-defined probability of correctness. We demonstrate that in return for erroneous behavior, significant energy and performance gains can be realized through probabilistic arithmetic (units)—over a factor of 4.62X in the context of an FIR filter used in a H.264 video decoding—where the gains are quantified through the energy-performance product (or EPP). These gains are achieved through a systematic probabilistic design methodology enabled by a design space spanning the probability of correctness of the arithmetic units, and their associated energy savings. [ABSTRACT FROM AUTHOR]

The use of oversampling to reduce I/O requirements of time-todigital converters for arrays of high precision photonic detectors is considered. Simulation results show that the high linearity offered by oversampled converters can be applied to time estimation. The averaging and lowpass filtering inherent in these techniques reduce jitter and enhance estimates of mean time delay. The effect of background illumination on the accuracy of time-of-flight estimates for Lidar range-finding is modeled using a first order sigma-delta modulator. Novel event-driven techniques are proposed for the reduction of sensitivity to background light level. [ABSTRACT FROM AUTHOR]

The stringent performance requirements of many infrared imaging applications warrant the development of precision high dynamic range, high speed focal plane arrays. In addition to achieving high dynamic range, the readout circuits for these image sensors must achieve high linearity and SNR at low power consumption. We first review four high dynamic range image sensor schemes that have been developed for visible range imaging and discuss why they cannot meet the stringent performance demands of infrared imaging. We then describe a new dynamic range extension scheme, Folded Multiple Capture, that can meet these performance requirements. Dynamic range is extended using synchronous self-reset while high SNR is maintained using few non-uniformly spaced captures and least-squares fit to estimate pixel photocurrent. We conclude with a description of a prototype of this architecture targeted for 3D-IC IR focal plane arrays. [ABSTRACT FROM AUTHOR]

We consider a transistor based approach for DNA detection. Immobilization of DNA at different positions of poly(l-lysine) coated field effect transistor arrays is achieved by deposition with a microspotting device or specific hybridization between complementary oligonucleotide sequences. The current voltage characteristics of the transistors are measured with the sample surface immersed in aqueous solution. The chapter provides a brief overview of our experimental technique and of its applications to the detection of DNA adsorption and hybridization. [ABSTRACT FROM AUTHOR]

This paper intends to provide a brief survey of the most advanced implementations of molecular analysis tools based on microtechnologies and to discuss a new approach for the development of integrated molecular analysis. The technique presented hereafter combine a labelfree method for molecular characterization based on UV absorbance and two technologies of silicon photodetectors addressed to fulfill the requirements of different applications. [ABSTRACT FROM AUTHOR]

This paper describes the design of a high-speed CMOS sample and- hold (S/H) circuit for pipelined analog-to-digital converters (ADCs). This S/H circuit consists of a switched-capacitor (SC) amplifier and a comparator to generate the mixed-mode sampled output data, which are represented both in analog and digital forms. The mixed-mode sampling technique reduces the operational amplifier (op amp) output swing. As a result, the requirements on op amp DC gain, slew rate and bandwidth are relaxed; the linearity of the SC amplifier is also improved. The reduction of signal swing in the front-end also brings benefit to the pipelined stages in speed and power consumption. The aperture errors at high frequency are minimized by time constant matching and digital error correction logic in the pipelined ADC. Designed in a 0.18-µm CMOS process, the proposed S/H circuit operates up to 200-MSample/s with a total harmonic distortion (THD) less than -60 dB and a signal-to-noise and distortion ratio (SNDR) larger than 59 dB in the worst-case simulation. The power consumption of the mixed-mode S/H circuit is 3.6-mW with 1.8-V supply voltage. [ABSTRACT FROM AUTHOR]

As technology scales, variability will continue to become worse. Random dopant fluctuations, sub-wavelength lithography, and dynamic variations due to circuit behavior will look like inherent unreliability in the design. Increasing soft errors will increase intermittent error rate by almost two orders of magnitude. As transistors scale even further, degradation due to aging will become worse. We discuss these effects and propose solutions in microarchitecture, design, and testing, for designing with billions of unreliable components to yield predictable and reliable systems, with probabilistic and statistical design methodology. [ABSTRACT FROM AUTHOR]