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This paper explores the design and hardware efficient realization of low complexity filter bank-based reconfigurable channelizers suitable for wireless receivers. The reconfigurability is achieved by deriving a set of non-uniform filter banks with different sampling factor combinations from a low complexity partial cosine modulated uniform filter bank, by combining different number of its neighbouring channels. The hardware complexity comparison of the filter bank channelizer designed by the proposed approach, with the existing works proves that this approach requires less number of multipliers in its realization to extract the same set of communication standards. To reduce the power and complexity of the multipliers needed for the hardware realization of the filter coefficients, an approximation algorithm, which increases the zeros in the binary represented filter coefficients is employed. The synthesis results show that the algorithm offers a considerable reduction in the hardware and power consumptions of the filter bank.

This paper presents a reconfigurable frequency response masking (FRM) wideband channelizer architecture which is characterized by low computational and hardware complexity. The proposed hardware efficient architecture is realized by incorporating resource shared non-maximally decimated filter bank in the implementation of the FRM wideband channelizer structure. The coefficients of the proposed architecture are optimized and made multiplier-free using Pareto based meta-heuristic algorithm in the canonic signed digit (CSD) space for reducing the total power consumption of the architecture. The architecture is finally designed and synthesized using Xilinx Vivado and Cadence RTL Encounter compiler for the area and power analysis and is compared with existing channnelizer architectures. The comparison highlights the advantages of the proposed architecture in terms of hardware complexity, power and workload in realizing sharp wideband channel filters.

This paper proposes the realization of perceptual wavelet approximation of Bark scale using a linear-phase integer decimated non-uniform filter bank (IDNUFB), designed by merging the channels of a partially cosine-modulated uniform filter bank. In effect, the channels with different sampling factors of the IDNUFB can be derived from the same prototype filter using the proposed method of design. Also, the proposed IDNUFB is employed for the realization of Bark frequency partitioning. The proposed method of IDNUFB design using PCM and merging is found to have linear-phase property and reduced hardware complexity, when compared to the existing filter bank-based methods for Bark frequency partitioning.

This paper proposes the design and analysis of different rational decimated non-uniform filter banks (RDNUFBs), in which channels with different rational sampling factors are derived by merging the channels of an initial RDNUFB. The feasibility of the merged RDNUFB is analyzed in terms of frequency selectivity, aliasing cancellation, phase distortion, and amplitude distortion. The necessary conditions for the resultant filter bank to be alias free and to possess the linear phase property, are derived. The proposed reconfigurable RDNUFB is deployed to extract various communication standards in the software defined radio (SDR) channelizer, and is found to reduce the hardware complexity when compared to other filter bank based SDR channelizers, when a large number of channels are extracted.

This paper proposes a multiplexer based technique for accelerating matrix vector multiplication (MVM) in long short term memory networks. The concept of multiple constant multiplication with separate generation and selection of partial products is used in this design. The most important benefit of the proposed architecture is the reduced implementation complexity in terms of cell area and power efficiency. A truncating method is effectively utilized with a guaranteed reduction in the hardware complexity and power consumption. For inner product computations, the input coefficients are truncated instead of being shifted, which in turn make use of combinational circuits replacing the sequential designs. Also, to improve the overall clock period, a novel design for inner product computations is envisaged, which uses modified multiplexer architecture instead of the existing method. The results show a reduction in the implementation complexity of the MVM with a significant power reduction of 14%.

In this brief, a power efficient reconfigurable non-maximally decimated filter bank-based modified frequency response masking technique is proposed to generate sharp transition width channels for wideband applications. The structure enables cost and power efficient processing of wideband signals. The main benefit of the proposed scheme is that the computational workload and hardware complexity of the modified frequency response masking technique is considerably less than that of the approaches existing in the literature. The hardware complexity of the design is further reduced by joint optimization of all the canonical signed digit represented filters using Pareto-based meta-heuristic algorithm.

Digital hearing aids can be made less expensive if they are reconfigurable and of low hardware complexity. Hence, this work proposes a hardware-efficient, reconfigurable filter bank structure, based on fractional interpolation. The proposed structure is reconfigurable since a single structure can be used for different patients with different types of hearing impairments. The proposed structure consists of a masking stage and a scheme generation stage with a prototype filter in each stage. The prototype filters are made multiplier-less by representing their coefficients in the CSD space. The filter characteristics are improved by deploying a MOABC optimization algorithm. The number of adders is reduced using the SIDC-CSE technique. The low-complexity structure can be used for all types of hearing impairments, with the matching error and delay within tolerable ranges. The proposed structure has been implemented on an FPGA to support the analytical results for low hardware complexity and hence low power.

This paper presents a multiplier-free realization of the block finite impulse response (FIR) filter in transpose form configuration using binary constant shifts method (BCSM). The proposed architecture is synthesized using Xilinx Vivado and Cadence RTL Encounter compiler for the area and power analysis and is compared with the existing works in the literature. The comparison highlights the advantages of the proposed architecture in terms of power, hardware complexity and throughput for realizing reconfigurable high throughput block FIR filters.

This paper describes the details of development of a hand held security device to help the security people at the entrances of big institutions/industries/apartments. The security people can scan the number plate of vehicles come at entrance using this device and the device will display whether the vehicle is authorised or unauthorised to enter to the premises. Provision is given to add/remove the registration number to/from the database. This device is designed around onboard computer, which is commonly termed as Raspberry Pi. The optical character recognition (OCR) technique implemented on this device is used for the identification of the registration number.

In this paper, two new inaccurate adder circuits are proposed. The proposed adder circuits are found to have less area and error rate. They are analyzed in terms of error metrics, delay, area, and power, and compared with those of conventional adders. A linear phase direct form finite impulse response filter is implemented using the proposed inaccurate adders, and performance is evaluated. It is shown that by using a combination of accurate and proposed inaccurate adders, the power consumption can be reduced, without much degradation in the filter performances.

In this paper, two reconfigurable architectures based on frequency-response masking (FRM) and non-maximally decimated filter bank system are proposed. The proposed methods are suitable for sharp wideband channelizers. The basic FRM structure consists of an interpolated modal filter and its masking filters. In both the proposed methods, the masking filters are synthesized by means of reconfigurable non-maximally decimated polyphase filter bank system. The second proposed method also exploits the LTI property of the FRM filter. The methods are beneficial when the number of bandwidths to be realized is large. The effective reduction in the multipliers and adders helps in reducing the hardware size. Both the methods are found to reduce the number of operations per second and hence the power consumption, when compared to the existing methods.

A low complexity digital reconfigurable filter bank structure which is suitable for digital channelizers in software defined radio is proposed in this paper. In order to get a sharp transition width with low hardware complexity, multiplicative finite impulse response (MFIR) filter is used as the prototype filter in the proposed structure. A masking stage and a channel generation stage constitute the two stages of the proposed structure. In the masking stage, 5 sub-bands are generated by performing cosine modulation technique on the prototype filter. In the channel generation stage, different channels are generated by doing spectral addition/subtraction operations on the interpolated versions of the MFIR filter. Hence, the basic techniques used in the proposed structure are, cosine modulation and fractional interpolation technique. By adjusting a 3-bit control signal, different regions and channels, generated by the two stages, can be obtained. The proposed structure has a hardware complexity, which is much lesser than that of the state-of-the art techniques used for SDR channelizers. The number of channels generated using the proposed structure is also more. The main advantage of the proposed structure is that the hardware complexity of the proposed structure remains the same even if the number of channels is increased.

This paper proposes a reconfigurable digital filter bank structure, which is suitable for designing hearing aids for most types of hearing losses. The proposed structure exploits the fractional interpolation and symmetry property of linear phase filters. The structure has two stages; the first one is called masking stage and the second one is called multiple passbands generation stage. The second stage i.e., multiple passband generation stage has 2 levels. By adjusting a 7-bit control signal, different sub-bands generated by the two stages can be obtained for audiogram matching. The number of sub-bands can be increased by increasing the number of fractional interpolated filters in level 2 of the multiple passbands generation block. Using the proposed structure, various types of audiograms can be matched with acceptable delay and matching error. The merits of the proposed structure are low hardware complexity and good audiogram matching with tolerable matching error and acceptable delay, when compared to the state of the art techniques for audiogram matching. Moreover, it is a reconfigurable structure. FPGA implementation of the proposed structure is also done to supplement the theoretical claim for low hardware complexity and power.

In this paper, a new multiplier-free transformation is proposed for the design of low complexity two dimensional (2D) finite impulse response (FIR) filters with improved circularity at wideband radii. By designing the 1D filter multiplier-free and using proposed multiplier-free transformation, a 2D circularly symmetric multiplier-free filter can be realized. Accuracy of the circular contour is measured based on contour approximation error. To prove the hardware efficiency of the proposed transformation, a 2D band-pass filter and a low-pass filter are designed and the overall complexity in terms of the number of multipliers required to implement the 2D filters is compared. From the results it is clear that the proposed transformation have good circularity at wideband radii and have less implementation complexity.

A computationally efficient maximally decimated filter bank core, suitable for digital hearing aids is designed and implemented in this work. The main advantages of the proposed design method are that the computational complexity and delay are less than that of the other filter bank based architectures in the literature. To reduce the hardware complexity of the filter bank core, filter coefficients are optimized and are implemented multiplier-free.

Inexact computing may be employed to reduce power and area in applications where, a small error in computations, does not affect the performance of the system. This paper proposes inexact half-subtractor and full-subtractor circuits, in which, the error occurs only in 25% of all the input combinations. The area and power of the proposed inexact half-subtractor are found to reduce by 25% and 39.37% respectively, with the error in difference occurring only in one input combination out of four. The area and power of the proposed full-subtractor are reduced by 50% and 71.53% respectively with the error in difference occur only at two input combinations out of eight. The proposed inexact subtractors and adders are used for the implementation of reconfigurable FIR filters using vertical horizontal common subexpression elimination (VHCSE) in the canonical signed digit (CSD) space. The area, power, and cell utilization are analyzed and found to reduce compared to the existing CSD based VHCSE algorithm. The performance of the proposed FIR filter is also analyzed in terms of pass-band ripple and stop-band attenuation and found to be within the tolerable limits.

In this paper, the use of sensor networks in environmental monitoring, vehicle monitoring and traffic management, which are important in a smart city are discussed. Sensors in Zigbee and Wi Fi networks form the back bone of this work. Low power networks like Zigbee and connectivity provided by WiFi are needed to realize the concept of Internet of Things (IoT). The main cause of environmental pollution in most cities are industries and automobiles emitting poisonous gases. This paper discusses the implementation of a unit which senses the presence of such gases and uploads the information to a website, and also sends messages to the concerned people. The second part of this work is a vehicle monitoring unit, that can be fixed in vehicles. This system tracks the location of the vehicle, detects accidents to the vehicle and monitors its engine temperature and the presence of poisonous gases from its exhaust. In the case of the vehicle is stolen, it also has the feature to locate the vehicle and prevent it from moving until a message is sent by the owner. The third part of the work, in which, vehicles which do signal jumping are detected and penalised. This feature is very relevant to the countries like India where traffic rules are regularly violated. The density of the traffic around traffic junctions is measured and information updated in the website. An Android app is developed so that all the required information is easily available. The paper describes the hardware and software implementation of the prototype system.

In today’s world, security threats for vehicles are on a constant rise and hence the necessity for ensuring safety for automobiles is of prime importance. Over speeding in accident prone areas is a major cause of road accidents. Accident rates are higher in some areas like school zones, hilly areas, highways, slippery terrains etc. It is in this context that Intelligent Transport Systems is an important and developing field. In this work, the conventional networks GSM and GPS have been used along with sensors positioned in the vehicle. Parking issues are another serious issue which needs attention. This is highly challenging because of the fact that a typical modern automobile doesn’t contain any systems in place to make parking easy. Thus, the objective of this work is to create a vehicular tracking system to ensure the safety of the vehicle and an efficient Automatic Parking system wherein parallel parking is done autonomously and efficiently.

The significant advantage of modified discrete Fourier transform (MDFT) filter banks over the conventional discrete Fourier transform (DFT) filter banks is the structure inherent alias cancellation in the former. When the number of channels is increased, the filters in the filter bank need to be of sharp transition width. This increases the complexity of the filters and hence that of the filter bank. Frequency Response Masking (FRM) approach is known to reduce the complexity of sharp transition width filters. This paper proposes a method to realize MDFT filter banks using FRM with much lesser complexity. To further reduce the complexity, the filter banks are made totally multiplier-less. This is done by converting the coefficients to the canonic signed digit (CSD) representation. Metaheuristic algorithms are used to improve the performance of the CSD represented filter banks. Modified integer coded genetic algorithm, differential evolution, artificial bee colony, harmony search and gravitational search algorithms are proposed to be used for the optimization of the proposed multiplier-less MDFT filter banks. This design method reduces the complexity, power consumption and chip area for the implementation of the uniform filter banks.

Low complexity and reconfigurability are reported to be the key features in a software defined radio (SDR). To obtain these features, a reconfigurable architecture based on frequency response masking (FRM) technique can be used for the implementation of the channel filters in the SDR. The frequency response masking approach is proved to be a good candidate for the realization of a sharp digital finite impulse response (FIR) filter with low complexity. To reduce the complexity and power consumption for hardware realization, a design method which makes the channel filters totally multiplierless is proposed in this paper. Continuous filter coefficients are first converted to finite precision coefficients using signed power of two (SPT) space to obtain a multiplier-less filter. The representation of the FRM filter coefficients in the SPT space can degrade the filter performance. This calls for the use of a suitable optimization technique. The classical gradient based optimization techniques cannot be deployed here, because the search space consists of integers. In this context, meta-heuristic algorithm is a good choice as it can be tailor made to suit the problem under consideration. They are especially useful in finding near optimal solutions in multimodal, multidimensional space. Several meta-heuristic algorithms are modified in this paper to be used for the discrete optimization.