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Electromigration (EM) is a severe reliability issue in power grid networks. The via array possesses special EM characteristics and suffers from Joule heating and current crowding, closely related to EM violations. In this study, a power grid EM analysis method was developed to solve temperature variation effects for the via array EM. The new method is based on the temperature-aware EM model, which considers the effects of self-heating and thermal coupling of interconnected lines in a power grid. According to the model, the proposed methodology introduces a locality-driven strategy and current tracking to perform full-chip EM assessment for multilayered power grids. The results show that temperature due to Joule heating indeed has significant impacts on the via EM failure. The results further demonstrate that the proposed method might reasonably improve efficiency while ensuring the accuracy of the analysis.

Rapid single-flux-quantum (RSFQ) circuits are developing rapidly, but there are still many layouts that need to be completed manually, greatly reducing the design efficiency. We report the shape constraints of Josephson transmission line (JTL), and then propose automatic placement and routing methods for RSFQ circuits. First, for the pipeline structure of concurrent-flow clocking, a detailed placement algorithm based on simulated annealing is proposed, which use D Flip-Flop (DFF) insertion, column placement, and intra-column perturbation strategies to ensure the synchronization of clock phase while completing the placement of logic cells. More importantly, for the shape constraints of JTL, a new two-step JTL routing method is proposed. The first step is dummy wire routing, and the shape violations and routing congestion caused by shape constraints are solved to search legal paths for JTL routing; in the second step, timing optimization is performed when replacing dummy wire with JTL cells. Experimental results show that the proposed automatic methods achieve a 5% area-reduction and a 20× speed-up compared to manual design.

Many Trojan detection technologies are too time-consuming to cover the entire state space in complex designs. The valuable verification resources should be allocated to regions vulnerable to security threats. However, there are few studies on security verification resources allocation. To fill in this gap, we design a security game framework to guide the security verification resources allocation. The framework utilizes the Trojan vulnerability measurement as player utilities, so the utility value determination doesn't need any expert prior knowledge to the specific design under test. A new Stackelberg security game specific to hardware security is also proposed. The new game model minimizes the defender utility loss with the limited verification resources restriction. Due to the lack of study on RTL Trojan vulnerability measurement, we also propose a RTL security vulnerability measurement to measure each logic propagation path vulnerability quantitatively and efficiently. We apply the proposed Stackelberg security game framework to Trust-hub Trojan benchmarks written by Verilog RTL code. The experiments demonstrate that the most suspicious logic propagation path is one part of Trojan in most cases and the proposed RTL security vulnerability measurement is effective. Also, the allocation strategy calculated by security game could get security confidence as high as possible with all available resources and may also cover the Trojan even when the carefully design Trojan evade the vulnerability measurement.

Paper-based digital microfluidic biochips (P-DMFBs) have recently emerged as a promising low-cost and fast-responsive platform for biochemical assays. In P-DMFBs, electrodes and control lines are printed on a piece of photograph paper using an inkjet printer and carbon nanotubes (CNTs) conductive ink. Compared with traditional digital microfluidic biochips (DMFBs), P-DMFBs enjoy significant advantages, such as faster in-place fabrication with printer and ink, lower costs, and better disposability. Since electrodes and CNT control lines are printed on the same side of this paper, a critical design challenge for P-DMFB is to prevent control interference between moving droplets and the voltages on CNT control lines. Control interference may result in unexpected droplet movements and thus incorrect assay outputs. To address this design challenge, a control-fluidic codesign methodology is proposed in this paper, along with two demonstrative design flows integrating both fluidic design and control design, i.e., the droplet-oriented codesign flow and the electrode-oriented codesign flow. The droplet-oriented flow is suitable for designing biochips with sparse electrodes and relatively larger number of droplets, whereas the electrode-oriented flow is suitable for biochips with dense electrodes and smaller number of droplets. The computational simulation results of real-life bioassays demonstrate the effectiveness of the proposed codesign flows.

In this paper, we note that the hardware Trojans that leak information through the unspecified output pins are difficult to detect by functional testing or side-channel signal analysis. Especially, the Trojans that leak the information through the side channel has proven stealthy to be detected. To solve this problem, we propose a feature matching method based on information flow tracking at high abstraction level. In this paper, the Trojans features are summarized with the format of high-level information flow tracking, which can be used to detect the Trojans. Experimental results show that our method can successfully identify the above-mentioned Trojans from Trust-hub, DeTrust, and OpenCores in less than 20 ms, showing significantly lower time complexity compared with the existing works.

Since the first circuit obfuscation technique was proposed to thwart reverse engineering (RE) attacks to integrated circuits (ICs), there have been active research in de-obfuscation attacks and new obfuscation countermeasures. Although it is crucial for an obfuscation method to be secure against known de-obfuscation attacks, it is equally important to keep the cost of circuit obfuscation low. Most importantly, obfuscation methods need to be formally analyzed for their effectiveness and efficiency. In this paper, we propose a set of quantitatively evaluable metrics for this purpose, particularly facilitated by a recently proposed circuit partition attack (CPA) and the powerful SAT-based attack (SATA). Moreover, we find that CPA can be applied prior to any de-obfuscation attacks to reduce RE efforts exponentially. We then propose a new equivalent class guided obfuscation scheme (ECG-Obfus) to defeat CPA which leverages specially designed camouflaged cells to replace judiciously selected logic gates. Specifically, we select candidate gates for obfuscation from one certain equivalent class, in which the underlying equivalent relation is defined based on IC topological structure information. We evaluate ECG-Obfus using the proposed metrics and conduct experiments on ISCAS 85/89 standard benchmark suites and OpenSparc T1 microprocessor. The results show that ECG-Obfus gains good resilience against known de-obfuscation attacks (including CPA and SATA), with low design complexity and performance overhead.

Facial landmark detection aims at locating a sparse set of fiducial facial key-points. Two significant issues (i.e., Intra-Dataset Variation and Inter-Dataset Variation) remain in datasets which dramatically lead to performance degradation. Specifically, dataset variations will lead to severe over-fitting easily and perform poor generalization in recent in-the-wild datasets which severely harm the robustness of facial landmark detection algorithm. In this study, we show that model robustness can be significantly improved by leveraging rich variations within and between different datasets. This is non-trivial because of the serious data bias within one certain dataset and inconsistent landmark definitions between different datasets, which make it an extraordinarily tough task. To address the mentioned problems, we proposed a novel Deep Coupling Neural Network (DCNN), which consists of two strong coupling sub-networks, e.g., Dataset-Across Network (DA-Net) and Candidate-Decision Network (CD-Net). In particular, DA-Net takes advantage of different characteristics and distributions across different datasets, while CD-Net makes a final decision on candidate hypotheses given by DA-Net to leverage variations within one certain dataset. Extensive evaluations show that our approach dramatically outperforms state-of-the-art methods on the challenging 300-W and WFLW dataset.

Flow-based microfluidic biochips are promising with significant applications for automating and miniaturizing laboratory procedures in biochemistry. Automated design methods for flow-based microfluidic biochips are becoming increasingly important due to the advancement in both integration scale and design complexity for complicated biochemical applications. Though the multilayer soft lithography fabrication provides flexibility to route both flow and control channels in any angle, existing routing algorithms still adopt Manhattan routing metrics, which design channel in either vertical or horizontal direction only. Moreover, based on the computational fluid dynamics analysis, rectilinear channels with 90° bends have the following issues: 1) reduced the fluidic flow rate, which degrades the performance of the biochip and may even result in the erroneous outcome of the whole procedure and 2) increased pressure at the right-angle bend, which negatively affects the reliability of the biochip. To fully utilize the routing flexibility, this paper proposes the first any-angle routing algorithm for flow-based microfluidic biochip, called AARF. Computational simulation results show that compared with traditional Manhattan routing method, the proposed AARF significantly improves the total wirelength and total effective wirelength (considering the turning angles) by 17.11% and 35.91%, respectively, which prove the effectiveness of the AARF routing flow.

Predicting the design rule check (DRC) violation hotspots in an early stage plays an essential role in the efficiency of the physical design. Multiple factors that affect the performance of a DRC hotspot predictor, among them, the efficacy of the extracted features plays a substantial role. In this paper, we propose a connectivity-based DRC hotspot prediction method using a convolutional neural network. We show that the proposed method is efficient in both training and prediction. The relation between pin features and predictor performance is further investigated and two weighted connectivity-based route map features are introduced. Experimental results demonstrate that the proposed algorithm can predict on average 73% of the DRC hotspots with only 2.7% false alarms.

Electromigration (EM) has been considered to be a severe reliability issue in power grid networks of large integrated circuits (IC). The via array possesses special EM characteristics that have been observed to be distinct from a single via. In this study, a compact analytical model for the fast estimation of EM for via array was proposed by calculating the current distribution in the via arrays. The proposed model was then analyzed in a multi-layer power grid, which, for the first time, considered the impacts of the current propagation that exists in the vertical via array connected within the multi-level interconnection to improve the accuracy of the analytical model further. According to the model, a novel methodology for full- chip EM checking for multi-layered power grids was proposed. This method factored in the routing structure of the multi-layer power grid network, ensuring the EM assessment analysis's efficiency for large-scale power grid networks without sacrificing accuracy.

Flow-based microfluidic biochips are attracting increasing attention with successful applications in biochemical experiments, point-of-care diagnosis, etc. Existing works in design automation consider the flow-layer design and control-layer design separately, lacking a global optimization and hence resulting in degraded routability and reliability. This paper presents a novel integrated physical co-design methodology, which seamlessly integrates the flow-layer and control-layer design stages. In the flow-layer design stage, a sequence-pair-based placement method is presented, which allows for an iterative placement refinement based on routing feedbacks. In the control-layer design stage, the minimum cost flow formulation is adopted to further improve the routability. Besides that, effective placement adjustment strategies are proposed to iteratively enhance the solution quality of the overall control-layer design. Experimental results show that compared with the existing work, the proposed design flow obtains an average reduction of 40.44% in flow-channel crossings, 31.95% in total chip area, and 22.02% in total flow-channel length. Moreover, all the valves are successfully routed in the control-layer design stage.

Detailed routing is an important stage in very large scale integrated physical design. Due to the extreme scaling of transistor feature size and the complicated design rules, ensuring routing completion without design rule checking (DRC) violations becomes more and more difficult. Studies have shown that the low routing quality partly results from nonoptimal net-ordering nature of traditional sequential methods. The concurrent routing strategy is always based on an NP-hard model, thus is at a disadvantage in runtime. In this paper, we present a novel concurrent detailed routing algorithm that routes all nets simultaneously. Based on the multicommodity flow model, detailed routing problem with complex design rule constraints is formulated as an integer linear programming. Some model simplification heuristics and efficient model solving algorithms are proposed to improve the runtime. Experimental results show that, the proposed algorithms can reduce the DRC violations by 80%, meanwhile can reduce wirelength and via count by 5% and 8% compared with an industry tool. In addition, the proposed algorithm is general that it can be adopted as an incremental detailed router to refine a routing solution, so the number of DRC violations that industry tool cannot fix are further reduced by 27%.

Intellectual property (IP) protection is one of the hardcore problems in hardware security. Semiconductor industry still lacks effective and proactive defense to shield IPs from reverse engineering (RE) based attacks. Integrated circuit (IC) camouflaging technique fills this gap by replacing some conventional logic gates in the IPs with specially designed logic cells (called camouflaged gates) without changing the functions of the IPs. The camouflaged gates can perform different logic functions while maintaining an identical look to RE attackers, thus preventing them from obtaining the layout information of the IP directly from RE tools. Since it was first proposed in 2012, circuit camouflaging has become one of the hottest research topics in hardware security focusing on two fundamental problems. How to choose the types of camouflaged gates and decide where to insert them in order to simultaneously minimize the performance overhead and optimize the RE complexity? How can an attacker de-camouflage a camouflaged circuit and complete the RE attack? In this article, we review the evolution of circuit camouflaging through this spear and shield race. First, we introduce the design methods of four different kinds of camouflaged cells based on true/dummy contacts, static random access memory (SRAM), doping, and emerging devices, respectively. Then we elaborate four representative de-camouflaging attacks: brute force attack, IC testing based attack, satisfiability-based (SAT-based) attack, and the circuit partition based attack, and the corresponding countermeasures: clique-based camouflaging, CamoPerturb, AND-tree camouflaging, and equivalent class based camouflaging, respectively. We argue that the current research efforts should be on reducing overhead introduced by circuit camouflaging and defeating de-camouflaging attacks. We point out that exploring features of emerging devices could be a promising direction. Finally, as a complement to circuit camouflaging, we conclude with a brief review of other state-of-the-art IP protection techniques.

Flow-based microfluidic biochips are attracting increasing attention with successful biomedical applications. One critical issue with flow-based microfluidic biochips is the large number of microvalves that require peripheral control pins. Even using the broadcasting addressing scheme, i.e., one control pin controls multiple microvalves simultaneously, thousands of microvalves would still require hundreds of control prins, which is unrealistic. To address this critical challenge in control scalability, the control-layer multiplexer is introduced to effectively reduce the number of control pins into log scale of the number of microvalves. There are two practical design issues with the control-layer multiplexer: (1) the reliability issue caused by the frequent control-valve switching, and (2) the pressure degradation problem caused by the control-valve switching without pressure refreshing from the pressure source. This paper addresses these two design issues by the proposed Hamming-distance-based switching sequence optimization method and the XOR-based pressure refreshing method. Simulation results demonstrate the effectiveness and efficiency of the proposed methods with an average 77.2% (maximum 89.6%) improvement in total pressure refreshing cost, and an average 88.5% (maximum 90.0%) improvement in pressure deviation.

Electromigration(EM) and power supply noise has been considered serious reliability issue in the power grid networks. Several performance goals in EM reliability optimization and power supply noise optimization are typically conflict with each other. In this paper, we propose a composite optimization method trading off EM and power noise optimization process. In the method, we expand a temperature-aware EM model, which takes EM transient effect into account. Experimental results show that composite reliability optimization method can lengthen the lifetime of an entire circuit by approximately 10% compared with previous respective optimization strategy and no power noise violations exists after the composite optimization.

Electromagnetic (EM) analysis is to reveal the secret information by analyzing the EM emission from a cryptographic device. EM analysis (EMA) attack is emerging as a serious threat to hardware security. It has been noted that the on-chip power grid (PG) has a security implication on EMA attack by affecting the fluctuations of supply current. However, there is little study on exploiting this intrinsic property as an active countermeasure against EMA. In this paper, we investigate the effect of PG on EM emission and propose an active countermeasure against EMA, i.e. EM Equalizer (EME). By adjusting the PG impedance, the current waveform can be flattened, equalizing the EM profile. Therefore, the correlation between secret data and EM emission is significantly reduced. As a first attempt to the co-optimization for power and EM security, we extend the EME method by fixing the vulnerability of power analysis. To verify the EME method, several cryptographic designs are implemented. The measurement to disclose (MTD) is improved by 1138x with area and power overheads of 0.62% and 1.36%, respectively.

As technology advances, there is a considerable gap between the congestion model used in global routing and the routing resource consumption in detailed routing. The new factors contributing to congestion include local pin access paths, vias, and various design rules. In this paper, we propose a practical congestion model with measurement of the impact of design rules, and resources consumed by vias and local pin access paths. The model is compatible with path search algorithms commonly used in global routing. Validated by full-flow routing, this congestion model correlates better with real resource consumption situation in detailed routing, compared with previous work. It leads to better solution quality and shorter runtime of detailed routing when it is used in the layer assignment phase of global routing stage.

Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional studies that handle this problem with clock routing or buffer insertion strategy, this paper proposes a novel register clustering methodology in generating the leaf level topology of the clock tree to reduce the power consumption. Three register clustering algorithms called KMR, KSR and GSR are developed and a comprehensive study of them is discussed in this paper. Meanwhile, a buffer allocation algorithm is proposed to satisfy the slew constraint within the clusters at a minimum cost of power consumption. We integrate our algorithms into a classical clock tree synthesis (CTS) flow to test the register clustering methodology on ISPD 2010 benchmark circuits. Experimental results show that all the three register clustering algorithms achieve more than 20% reduction in power consumption without affecting the skew and the maximum latency of the clock tree. As the most effective method among the three algorithms, GSR algorithm achieves a 31% reduction in power consumption as well as a 4% reduction in skew and a 5% reduction in maximum latency. Moreover, the total runtime of the CTS flow with our register clustering algorithms is significantly reduced by almost an order of magnitude.

As VLSI technology continuously scales down, buffered clock tree synthesis (CTS) has become increasingly critical in an attempt to generate a high-performance synchronous chip design. This paper presents a novel obstacle-avoiding CTS approach with slew constraints satisfied and signal polarity corrected. We build a look-up table through NGSPICE simulation to achieve accurate buffer delay and slew, which guarantees that the final skew after NGSPICE simulation is as satisfactory as expected. Aiming at skew optimization under constraints of slew and obstacles, our CTS approach features the clock tree construction stage with the obstacle-aware topology generation algorithm called OBB, balanced insertion of candidate buffer positions and a fast heuristic buffer insertion algorithm. With an overall view on obstacles to explore the global optimization space, our CTS approach effectively overcomes the negative influence on skew brought by the obstacles. Experimental results show the effectiveness of our CTS approach with significantly improved skew and latency by 69.0% and 72.0% on average. In addition, the accuracy of the look-up table is demonstrated through the huge skew reduction by 87.3% on average. Moreover, our OBB heuristic algorithm obtains 53.2% improvement in skew than the classic balanced bipartition algorithm.

In recent years, formal methods have been adopted to detect the hardware Trojans (HT). However, they generally suffer from the time-consuming and error-prone development for property, lack of self-learning system to counter with the future HT types, and high computational complexity due to the growth of design scales. To overcome the above limitations, we propose an automatic security property generation method (ASPG) by feature analysis and property matching techniques. Machine learning is applied to systematically training the property library from the suspicious behaviors in unknown designs, which is expected to counter with the future HT. To reduce the computational complexity, we transform the register-transfer level (RTL) code into an introduced succinct abstract format to remove the redundant information which is unnecessary for depicting HT features. Experimental results show that the properties are generated in less than 50 ms with low memory consumption and the benchmarks from Trust-hub and DeTrust can be successfully detected with 0 false negatives and positives.

Bibliotherapy has been proved to be an effective way to deal with adolescents psychological stress. Specific reading materials are provided to patients with physical or mental diseases for the purpose of prevention, healing, and rehabilitation. But traditional bibliotherapy requires professional staff with the background of both psychological and library services, which is quite demanding and labor consuming. Moreover, bibliotherapy based on paper books is getting ill-fitted in the present big data era. To address the limitations, this paper proposes an online reading recommendation system called TeenRead to carry out bibliotherapy for adolescents. TeenRead involves the management of users and articles, analysis of users' dynamic reading behaviors, as well as the recommendation based on users' stress categories, stress levels, and reading interests. The results of the user study on 10 volunteers show that, the average decrease of users' stress level is significantly dropped by 22% after a period of reading on TeenRead, which proves that TeenRead performs pretty well as a new method of bibliotherapy.

Wirelength is a traditional optimization objective in global placement algorithms. To eliminate cell overlaps, spreading forces need to be added to pull cells away from highly congested areas. At the same time, to optimize wirelength, the quadratic nature should be maintained. In this paper, several techniques are proposed to optimize spreading force orientation and modulation. Specifically, a percentage-driven method is proposed to cluster overfilled bins, followed by a center-uniformization algorithm to demarcate the expand region for the cluster. Finally, cells are distributed evenly within each expand region while maintaining relative cell positions and minimizing cell displacements. Experimental results show that the global placer that integrated with the proposed strategies achieves 13.0% and 2.1% less wirelength compared with Capo10.5 and Aplace3, respectively.

Circuit camouflaging is a layout-level technique to protect VLSI design from being attacked by reverse engineering. It hides design information by configurable logic units that can be configured to perform different functionalities with identical looks to the attackers. In this chapter, after introducing the primitive for gate camouflaging-based obfuscation, we analyze its vulnerability to one specific attack based on circuit partitioning. We then elaborate this attack and discuss two practical countermeasure methods. We explain that the security of gate camouflaging-based obfuscation not only depends on the number of gates being obfuscated, but also which gates we select for obfuscation and the number of different functionalities these gates can implement. As an example, we show how to perform a multiplexer-based gate camouflaging.

Efficient power grid analysis is critical for modern very large scale integration design but is computationally challenging in runtime and memory consumption because of the increasing size of power grids. PowerRush is proposed as an efficient IR-drop simulator, which includes an efficient SPICE parser, a robust circuit builder, and a linear solver Algebraic MultiGrid Preconditioned Conjugate Gradient. The proposed AMG-PCG solver is a pure algebraic method, which can provide stable convergence without geometric information. Aggregation-based AMG with K-cycle acceleration is adopted as a preconditioner to improve the scalability of iterative method. In multigrid scheme, double pairwise aggregation technique is applied to matrix graph in coarsening to ensure low setup cost and memory requirement. Furthermore, K-cycle multigrid scheme is adopted to provide Krylov subspace acceleration at each level to guarantee enhanced robustness and scalability. The experimental results for large-scale power grids have shown that PowerRush has remarkable scalability both in runtime and memory consumption. DC analysis of power grid with 60-million nodes can be solved by PowerRush for 0.01 $mV$ accuracy within 150 s and 21.99 GB total memory used. Moreover, the proposed AMG-PCG solver can perform much better than widely used direct solver Cholmod and well-developed Hybrid solver both on runtime and memory consumption.

Hardware security has become more and more important in current information security architecture. Recently collected reports have shown that there may have been considerable hardware attacks prepared for possible military usage from all over the world. Due to the intrinsic difference from software security, hardware security has some special features and challenges. In order to guarantee hardware security, academia has proposed the concept of trusted integrated circuits, which aims at a secure circulation of IC design, manufacture and chip using. This paper reviews the main problems of trusted integrated circuits, and concludes four key domains of the trusted IC, namely the trusted IC design, trusted manufacture, trusted IP protection, and trusted chip authentication. The main challenges in those domains are also analyzed based on the current known techniques. Finally, the main limitations of the current techniques and possible future trends are discussed.

Heterogeneous integration in modern System-On-Chips (SOCs) drives the design automation process for analog and mixed signal circuit components, where matching constraints for certain analog signals are critical for correct functionality. This paper presents a detailed routing solution for analog nets with the single-layer length matching constraint called LEMAR, i.e., a single-layer LEngth MAtching Router. LEMAR is a gridless router using a non-uniform grid routing model to ensure the length matching constraint. LEMAR has the following features: (1) an effective routing model is used for layout partitioning and wire detouring, (2) detouring patterns are presented to obtain the given detouring length, and (3) an enhanced A ⁎ search algorithm along with backtracking technique is presented for finding a routing solution with the length matching constraint. Experimental results are promising.

For 32/22nm technology nodes and below, double patterning (DP) lithography has become the most promising interim solutions due to the delay in the deployment of next generation lithography (e.g., EUV). DP requires the partitioning of the layout patterns into two different masks, a procedure called layout decomposition. Layout decomposition is a key computational step that is necessary for double patterning technology. Existing works on layout decomposition are all single-threaded, which is not scalable in runtime and/or memory for large industrial layouts. This paper presents the first window-based parallel layout decomposition methods for improving both runtime and memory consumption. Experimental results are promising and show the presented parallel layout decomposition methods obtain upto 21x speedup in runtime and upto 7.5xreduction in peak memory consumption with acceptable solution quality.

Circuit obfuscation techniques have been proposed to conceal circuit's functionality in order to thwart reverse engineering (RE) attacks to integrated circuits (IC). We believe that a good obfuscation method should have low design complexity and low performance overhead, yet, causing high RE attack complexity. However, existing obfuscation techniques do not meet all these requirements. In this paper, we propose a polynomial obfuscation scheme which leverages special designed multiplexers (MUXs) to replace judiciously selected logic gates. Candidate to-be-obfuscated logic gates are selected based on a novel gate classification method which utilizes IC topological structure information. We show that this scheme is resilient to all the known attacks, hence it is secure. Experiments are conducted on ISCAS 85/89 and MCNC benchmark suites to evaluate the performance overhead due to obfuscation.

Circuit camouflaging techniques have been proposed to thwart reverse engineering (RE) attacks to integrated circuits (IC). In one of the most well-known camouflaging methods, selective XOR, NAND, and NOR gates are replaced by configurable logic units which have the same appearance to the RE attackers. It is argued that a successful attack has to brute force search all the camouflaged gates' possible {XOR, NAND, NOR} combinations, resulting in the attack complexity exponential to the number of camouflaged gates. In this paper, we have reported an attack to significantly reduce this complexity by partitioning the IC to many subcircuits to attack individually. We validate the power of the proposed circuit partition based attack on IS CA S benchmark suite and OpenSparc T1 microprocessor, and propose a potential countermeasure to re-secure IC camouflaging.

Clock gating is one of the most effective techniques to reduce clock tree power. Although it has already been studied considerably, most of the previous works are restricted to either register transfer level (RTL) or clock tree synthesis stage. Clock gating design at RTL is coarse and it pays no attention to the physical information, therefore, it often results in large wirelength overhead. While if clock gating is considered only at clock tree synthesis, the optimization space is largely limited due to the fixing of registers. To fully use the logical and physical information between registers, we propose a new flow for low-power gated clock tree design in this work. It mainly includes three parts: gated clock tree aware register placement, gated clock tree construction, and incremental placement. Compared with the previous works on clock gating, our algorithm reduces the clock tree power with much fewer gating logics, therefore, the overhead to the placement is also reduced.

With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture (called Planar-CRX). Our Planar-CRX method integrates the extended deferred-merge embedding algorithm (DME-X, which extends the DME algorithm to X architecture) with modified Ohtsuki’s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.

This paper studies the impact of dummy fill for chemical mechanical polishing (CMP)-induced capacitance variation on buffer insertion based on a virtual CMP fill estimation model. Compared with existing methods, our algorithm is more feasible by performing buffer insertion not in post-process but during early physical design. Our contributions are threefold. First, we introduce an improved fast dummy fill amount estimation algorithm based on [4], and use some speedup techniques (tile merging, fill factor and amount assigning) for early estimation. Second, based on some reasonable assumptions, we present an optimum virtual dummy fill method to estimate dummy position and the effect on the interconnect capacitance. Then the dummy fill estimation model was verified by our experiments. Third, we use this model in early buffer insertion after layer assignment considering the effects of dummy fill. Experimental results verified the necessity of early dummy fill estimation and the validity of our algorithm. Buffer insertion considering dummy fill during early physical design is necessary and our algorithm is promising.

A W-shaped multilevel full-chip routing framework using W-shaped optimization flow is used to find the final routing solution. The W-shaped flow consists of two sequential V-shaped optimization flows. The first V-shaped flow optimizes the global routing solution. The probabilistic congestion prediction technique is used to guide the global routing decision to find the routing solution that evenly distributes the nets. Then, the second V-shaped flow improves the quality of the routing result. Tests on a set of commonly used benchmark circuits and comparisons with other multilevel routing systems show that the routability, total wire length, total number of vias, and the runtime are all improved.

It's a trend to consider the power supply integrity at early stage to improve the design quality. Specifically, floorplanning process is modified to improve the power supply as well. In the modified floorplanning process, both the floorplan and power/ground (P/G) network are adjusted to search for optimal floorplan as well as the most robust power supply. In this paper, we propose a novel algorithm to carry out this modified floorplanning. A new analytical method is proposed to estimate the voltage drop while the floorplan is varying constantly. This fast analytical voltage drop estimating method is plugged into the modified floorplanner to speed up the whole floorplanning process. Compared with previous methods, our algorithm can search for the optimal floorplan with consideration of power supply integrity more efficiently and therefore leads to better results. Furthermore, this paper also proposes a novel heuristic method to optimize the topology of P/G network. This optimization algorithm could construct a more robust power supply system. Experimental results show the method can speedup the IR-drop aware floorplanning process by about 10 times and reduce the routing area of P/G network while maintaining the floorplan quality and power supply integrity.

Multiple supply voltage (MSV) is an effective scheme to achieve low power. Recent works in MSV are based on physical level and aim at reducing physical overheads, but all of them do not consider level converter, which is one of the most important issues in dual-vdd design. In this work, a logic and layout aware methodology and related algorithms combining voltage assignment and placement are proposed to minimize the number of level converters and to implement voltage islands with minimal physical overheads. Experimental results show that our approach uses much fewer level converters (reduced by 83.23% on average) and improves the power savings by 16% on average compared to the previous approach [1]. Furthermore, the methodology is able to produce feasible placement with a small impact to traditional placement goals.

As process technology scales down to very deep sub-micron (VDSM) in semiconductor manufacturing technology, intrinsic size becomes close to or even shorter than the wavelength used for optical lithography. Thus, some distortions and deformations are introduced by optical proximity effects (OPE) mainly caused by the diffraction and interference of exposure light when layout patterns on a mask are transcribed to a wafer, which influence on the yield and performance of IC circuit. In order to compensate for the deformations, optical proximity correction (OPC) is the most commonly used methodology. Presently, the OPC method is to use a unitary toleration on the whole chip layer, which makes the run time of OPC algorithm longer, causes the size of GDSII files to follow exponential growth, and results in the cost of making mask grow immensely. Firstly, this paper proposes a self-adaptation OPC method with preprocessing function of patterns classification. According to the need of the correction precision, the OPC system divides patterns corrected into two groups with different toleration: critical patterns and general patterns, which enhance the efficiency of the OPC approach. Secondly, a model-based OPC method is presented based on pattern subsection and classification, which keeps the precision of the correction as well as enhances the efficiency. We also propose a rule-based OPC method with general, concise and complete correction rules, and achieve automatic-built rules-based and its looking-up. Thirdly, we also implement an OPC system, called MR-OPC; the MR-OPC system integrates both rule-based OPC and model-based OPC into a whole, so it can solve the confliction between the efficiency and precision. Experimental results show that the MR-OPC system we suggested has advantages of the efficiency and expansibility.

Power is the major challenge threatening the progress of very large scale integration (VLSI) technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actually strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result, incremental modifications are performed based on the clock skew specifications by moving registers toward preferred locations that may reduce the clock network size. At the same time, the side-effects to logic cell placement, such as signal net wirelength and critical path delay, are controlled. Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.

As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the most effective methods is based on clock gating to shut off the clock when the modules are idle. However, previous works on gated clock tree power minimization are mostly focused on clock routing and the improvements are often limited by the given registers placement. The purpose of this work is to navigate the registers during placement to further reduce the clock tree power based on clock gating. Our method performs activity-aware register clustering that reduces the clock tree power not only by clumping the registers into a smaller area, but also by pulling the registers with the similar activity patterns closely to shut off the clock more time for the resultant subtrees. In order to reduce the impact of signal nets wirelength and power due to register clustering, we apply the timing and activity based net weighting in [14], which reduces the nets switching power by assigning a combination of activity and timing weights to the nets with higher switching rates or more critical timing. To tradeoff the power dissipated by the clock tree and the control signal, we extend the idea of local ungating in [6] and propose an algorithm of gate control signal optimization, which still sets the gate enable signal high if a register is active for a number of consecutive clock cycles. Experimental results on a set of MCNC benchmarks show that our approach is able to reduce the power and total wirelength of clock tree greatly with minimal overheads.

A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router benefits from a novel cost function to compute critical areas during routing process, and heuristically lays the patterns on the chip area where it is less possible to induce critical area. The router also takes other objectives into consideration, such as routing completion rate and nets length. It takes advantage of gridless routing to gain more flexibility and a higher completion rate. The experimental results show that critical areas are effectively decreased by 21% on average while maintaining the routing completion rate over 99%.

Buffer insertion plays a great role in modern global interconnect optimization. But too many buffers exhaust routing resources, and result in the rise of the power dissipation. Unfortunately, simplified delay models used by most of the present buffer insertion algorithms may introduce redundant buffers due to the delay estimation errors, whereas accurate delay models expand the solution space significantly, resulting in unacceptable runtime. Moreover, the power dissipation problem becomes a dominant factor in the state-of-the-art IC design. Not only transistor but also interconnect should be taken into consideration in the power calculation, which makes us have to use an accurate power model to calculate the total power dissipation. In this paper, we present two stochastic optimization methods, simulated annealing and solution space smoothing, which use accurate delay and power models to construct buffered routing trees with considerations of buffer/wire sizing, routing obstacles and delay and power optimization. Experimental results show our methods can save much of the buffer area and the power dissipation with better solutions, and for the cases with pins ≤ 15, the runtime of solution space smoothing is tens of times faster.

In this paper, we present a novel pattern-based method to simulate large-scaled power/ground (P/G) grids. This method takes advantage of both traditional direct simulation methods and iterative simulation methods. The new method explores the geometry characteristics of regular P/G grids and translates topology similarity to submatrix regularity, which is called "pattern" in this paper. Such pattern structures can reduce the memory usage dramatically. Further, a new type of preconditioner is constructed to optimize the simulation process. Experimental results show that the proposed approach is about 5times faster than the previous iterative methods with much lower memory, and is superior to the macro model-based hierarchical method on the tested large cases with pattern structures

The voltage island style has been widely accepted as an effective way to design low power high performance chips. This paper proposes an automated voltage island generation flow in standard cell based designs. Two important objectives in voltage island designs are addressed in this flow: 1) reducing power dissipation under given performance constraints; 2) reducing implementation overheads, mainly layout overheads caused by cell clustering to form islands. The first objective is handled with timing and power driven netweighting and timing analysis in voltage assignment. For the second objective, we propose layout aware voltage assignment, i.e., voltage assignment during placement. We iteratively perform the following to adjustments: adjustment on voltage assignment to facilitate voltage island generation, and adjustment on cell locations to cluster cells in voltage islands. These iterations lead to a flow featured with tightly integrated voltage assignment and cell placement. Experimental results have demonstrated the advantages of our approach.

As VLSI technology continuously scales down, robust clock tree synthesis (CTS) has become increasingly critical in an attempt to generate a high-performance synchronous chip design. Clock skew resulted by process variations can be significantly different from the nominal value. In this paper, we propose an efficient buffer sizing algorithm to solve the skew optimization problem in presence of process variations. By analyzing the influence of process variations on wire delay and buffer delay, we make a quantitative estimation of the skew distribution under Monte-Carlo SPICE simulations. The number and size of buffers on some critical paths are rearranged to reduce the skew results under process variations. Experiment results which are evaluated on ISPD 2010 benchmarks show that our algorithm achieves a significant 58% reduction on worst skew with only 6% increase on power consumption.

In flow-based microfluidic biochips, microvalves on the control layer need to be connected to control pins via control channels. In application-specific and portable microfluidic devices, critical microvalves need to switch at the same time for correct functionality. Those microvalves are required to have equal or similar channel lengths to the control pin, so that the control signal can reach them simultaneously. This paper presents a practical control-layer routing flow (PACOR) considering the critical length-matching constraint. Major features of PACOR include: (1) effective candidate Steiner tree construction and selection methods for multiple microvalves based on the deferred-merge embedding (DME) algorithm and maximum weight clique problem (MWCP) formulation, (2) minimum cost flow-based formulation for simultaneous escape routing for improved routability, and (3) minimum-length bounded routing method to detour paths for length matching. Computational simulation results show effectiveness and efficiency of PACOR with promising matching results and 100% routing completion rate.

The chip-level design problem is critical in pin-constrained electrowetting-on-dielectric (EWOD) biochips, which not only affects the number of control pins and PCB routing layers from the manufacturing cost point of view, but also determines the functional reliability induced by excessive applied voltage. Existing works either greedily minimize the number of control pins with degraded routability, or disregard the differences in driving voltages on the electrodes, where the trapped charge due to excessive applied voltage causes significant reliability issue. This paper presents the first SVM-based classifier for electrode addressing in chip-level design stage, which simultaneously optimizes the number of control pins, routability, as well as reliability. Experimental results on both real-life chips and synthesized benchmarks show that, compared with the state-of-the-art method, the SVM-based electrode addressing method obtains significant improvements in both routability and reliability.

Clock networks dissipate a significant fraction of the entire chip power budget. In contrast to most of the traditional works that handle the power optimization problem with clock routing or buffer sizing, we propose a novel register clustering methodology for power reduction of clock trees. Moreover, a fast three-stage clock tree synthesis (CTS) approach based on register clustering is presented to verify the validity of the methodology. By comparison with the state-of-the-art low power CTS research works Contango2.0 [21] and the CTS of Purdue University [16], our three-stage CTS approach achieves 1.30×, 1.07× smaller power consumption while exhibiting 2.01×, 1.52× smaller skew. Furthermore, the runtime of our CTS approach is 17.36×, 8.16× shorter than that of [21] and [16] respectively.

Early stage power estimation is critical for SoC architecture exploration and validation in modern VLSI design, but real-time, long time interval and accurate estimation is still challenging for system-level estimation and software/hardware tuning. This work proposes a model abstraction approach for real-time power estimation in the manner of machine learning. The singular value decomposition (SVD) technique is exploited to abstract the principle components of relationship between register toggling profile and accurate power waveform. The abstracted power model is automatically instrumented to RTL implementation and synthesized into FPGA platform for real-time power estimation by instrumenting the register toggling profile. The prototype implementation on three IP cores predicts the cycle-by-cycle power dissipation within 5% accuracy loss compared with a commercial power estimation tool.

Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, a new hierarchical flow of 3-D floorplanning with a new inter-layer partitioning method. The blocks are partitioned into different layers before floorplanning. A simulated annealing (SA) engine is used to partition blocks with the objective of minimizing the statistical wirelength estimation results. The solution quality is not degraded by the hierarchical flow. Second, floorplans of all the layers are generated in a SA process. Original 3-D floorplanning problem is transformed into solving several 2-D floorplanning problems simultaneously. The solution space is scaled down to maintain a low design complexity. Finally, Experimental results show that our algorithm improves wirelength by 14%-51% compared with previous 3-D floorplanning algorithms. The hierarchical approach is proven to be very efficient and offers a potential way for high-performance 3-D design