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This paper presents a methodology for designing balanced VLIW architectures. Since we are interested in the architectural aspects of those processors we have developed a framework to evaluate the relationship among the main components of a VLIW machine. Our framework includes the simulator of an actual processor, software tools both to detect the instruction level parallelism of application programs and to generate the parallel object code for each specific machine configuration derived from our basic model of VLIW architecture, and an interpreter which reproduces the behavior of each member of the VLIW family. By interpreting the optimized code derived from a suite of benchmark programs, we have determined the best VLIW configuration for each test program. From these experiments we have discovered which relationship among the machine components should be observed during the specification of a VLIW machine in order to obtain a balanced processor.

Conventional processor can be characterized by the sequential nature in which machine instructions are dispatched: only one instruction is issued each time, and the next one will be started after the conclusion of the current one. However, the machine performance can be significantly improved if the hardware is able to issue several instructions to be executed simultaneously. In this work we describe some experiments that have been carried out to assess the effect of alternative instruction dispatching algorithms on the overall performance of machines comprising several independent functional units. The paper presents the main aspects of the project, and shows that reduction ratios up to 78% in the processing time required by some benchmark programs can be obtained by issuing multiple instructions.

This paper presents the specification and implementation of a kernel supporting an environment oriented towards the development and execution of parallel programs written in PASCAL. The host machine is a multiprocessor system with a common bus interconnecting the processing boards, the global memory segment, I/O boards, and other system modules. The processing board structure of the host is similar to the IBM-PC mother board. The environment is based on the TURBO PASCAL which was extended with constructs providing facilities to express and synchronise the parallel execution of processes. The paper describes the main issues regarding the specification and implementation of the kernel, and outlines the use of the environment in the development of parallel programs.

The gap between memory and processor speeds is responsible for the substantial amount of idle time of current processors. To reduce the impact provoked by the so-called "memory gap problem," many, software techniques (e.g., the code layout reorganization) together with hardware mechanisms (cache memory, translation look-aside buffer branch prediction, speculative execution, trace cache, instruction reuse, and so on) have been successfully implemented. In this paper we present some experiments that explain why these mechanisms and techniques are so efficient. We found that only a small fraction of the object code is actually executed: our experiments disclosed that more than 50% of the instructions remain untouched during the whole execution, and the percentages of basic blocks which remain unused are slightly greater. In addition to the usage of instructions and blocks, the paper provides further insights regarding the behavior of application programs, and gives some suggestions for extra performance gains.

This paper describes the design and implementation of a virtual machine oriented towards the execution of concurrent programs written in the high level language EDISON defined by P. Brinch Hansen in [1] and [2]. The target machine specification includes primitives reflecting typical constructs of source programs. For instance, there are primitives realizing directly those source operations involving array type and set type variables; instructions to create, synchronize, and to kill processes etc. As required by the source language, the virtual machine implements the concept of Conditional Critical Regions [3]. EDISON programs are translated to target code before their actual interpretation. Some virtual machine interpreters were implemented: first we developed two interpreters in high level language; next an interpreter in ASSEMBLY language; and finally we implemented a μ-programmed version of the virtual machine. Some performance figures of the interpretation are included in the appendix.

In an earlier work we have introduced an Architecture Description Language (ADL for short) and its support system implemented in a machine-independent fashion [5]. This system provides facilities for teaching and research in computer architecture: target machines described in ADL are fed into the support system, and the corresponding interpreter programs are automatically generated. These programs reproduced the run-time environment of the target, as specified by the ADL description, including the interpretation of the target code. This paper presents a brief review of the language and the implementation of its support system. Next, the new constructs that have been incorporated into ADL to give an extended version (ADL-X) are described. Through these mechanisms, designers can specify and synchronize target machine activities occuring in parallel. Finally, we show how the new support system is being implemented, and give a description of a pipeline machine, using the new language features.

This paper presents the specification and implementation of a kernel supporting an environment oriented towards the development and execution of concurrent programs written in an extension of PASCAL. The environment is based on the TURBO PASCAL which was extended with constructs providing mechanisms to express and synchronize the concurrent execution of processes. In addition to the specification and implementation details of the kernel, the paper also outlines the use of the environment in the development of parallel programs, and describes the current stage of the work which should lead to the migration of the environment to a parallel host machine.

The specification and implementation of a machine oriented to the execution of programs written in applicative languages is presented. Source programs are translated into a intermediate form which is interpreted by the target architecture: a normal graph reduction machine based on combinators. Some interpreters for this reduction machine were implemented. In this way, we developed interpreters in the C language, in ASSEMBLY language, and finally a microprogrammed version of the target architecture. The paper shows the relevant aspects of the reduction machine design and the current stage of the project.