Search

We measure the Casimir force gradient between silicon surfaces with nanoscale, rectangular corrugations and a gold sphere attached to a micromechanical torsional oscillator. By comparing the force gradients on the corrugated surfaces to that on a smooth, flat surface of the same material, we demonstrate that the Casimir force deviates from the value expected from the pairwise additive approximation and the proximity force approximation. The observed deviation qualitatively agrees with calculations that take into account the interplay between finite conductivity and geometry effects. However, the agreement is not exact, possibly due to uncertainties in the optical properties of the silicon substrate.

We have fabricated and tested the performance of sub-50nm gate nMOSFETs to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. For a 30nm×40 μm×2 device, we found f(T) =465GHz at V(ds)=2V, V(g)=0.67V, which is the highest cut-off frequency reported for a MOSFET produced on bulk silicon substrate so far. However, our measurements of f(max) and noise figure indicate that parasitics impose limitations on SHF operation. We also present a high-frequency ac model appropriate to sub-50nm gate length nanotransistors, which incorporates the effects of the parasitics. The model accurately accounts for measurements of the S and Y parameters in the frequency range from 1 to 50GHz.

We have fabricated and demonstrated a new device called the vertical replacement-gate (VRG) MOSFET. This is the first MOSFET ever built in which: (1) all critical transistor dimensions are controlled preciselywithout lithographyand dryetch, (2) the gate length is defined bya deposited film thickness, independentlyof lithographyand etch, and (3) a high-qualitygate oxide is grown on a single-cry stal Si channel. In addition to this unique combination, the VRG-MOSFET includes self-aligned source/drain extensions (SDEs) formed bysolid source diffusion (SSD), small parasitic overlap, junction, and source/drain capacitances, and a replacement-gate approach to enable alternative gate stacks. We have demonstrated nMOSFETs with an initial VRG process, and pMOSFETs with a more mature process. Since both sides of the device pillar drive in parallel, the drive current per lm of coded width can far exceed that of advanced planar MOSFETs. Our 100 nm VRG-pMOSFETs with tOX ¼ 25 A drive 615 lA/lm at 1.5 V with IOFF ¼ 8 nA/lm—80% more drive than specified in the 1999 ITRS Roadmap at the same IOFF. Our 50 nm VRGpMOSFETs with tOX ¼ 25 A approach the 1.0 V roadmap target of ION ¼ 350 lA/l ma tIOFF ¼ 20 nA/lm without the need for a hyperthin (

The exponential growth of the silicon industry can be attributed to that fact that silicon has a native oxide that is silicon dioxide. With SiO 2 soon approaching its fundamental limit, we must find an alternate to SiO 2 or a new switch to replace MOSFETs. In this paper we focus on the leading alternate gate dielectrics. We first discuss the selection criteria for alternate gate dielectrics and why it is important to have an amorphous gate dielectric. SiO 2 and aluminum oxide remain amorphous at very high temperatures. For dielectrics with K >15 and gate power 2 , it may be necessary to stabilize the amorphous phase of metal oxides by adding Al or Si to the oxide, thus forming multi-component dielectrics such as aluminates. We then benchmark aluminates with aluminum oxide and silicon dioxide.

A multiple exposure technique is used to print various types of patterns with critical dimensions much smaller than the wavelength of light used for exposure. The process latitude of the exposure can be very large because it is limited by the large pattern of the individual mask and not by the critical dimension of the small feature.

A method for optimizing the electron optics of the SCALPEL exposure tool is described. The method uses the SCALPEL mark detection method with a grating mark as an aerial image monitor. The root-mean-square deviation of the recorded backscattered electron signal from an ideal triangle waveform was used as a measure of the image fidelity, scale and orientation. The resolution of the technique is limited only by signal-to-noise and the fidelity of the marks. Experiments were performed using 2 @mm period grating marks that were fabricated in a SiO"2/WSi"2 structure using SCALPEL lithography and plasma processing. The projector lenses and magnification/rotation coils were optimized. For these experiments the measured resolutions for determining focus (@df), magnification (@dM), and rotation (@d@q) of a 250 @mm X 250 @mm field were @df ~ +/-1 @mm, @dM ~ +/-15 ppm and @d@q ~ +/- 0.1 mrad. A straightforward path to improving these results is described.

Alternating phase shift technology has been shown to substantially improve focus latitude and resolution for several years. However, the use of phase shift masks to improve the process latitude in gate level lithography has been hindered by the lack of commercially available tools that can convert conventional gate layouts into phase shift mask patterns. A software package has recently become available that allows a user to create phase shift masks to reduce the gate length of features in existing circuit layouts. A digital signal processing chip with 2 million gates has been used as a test vehicle to evaluate the feasibility of phase shifting and processing a large number of devices in a complete circuit. Three wafer lots have been processed with a target feature size of 120 nm with a variation of 25 nm 3σ. The timing circuits of the chips have been tested; those with 120 nm gates showed a nearly fourfold improvement in speed when compared to 240 nm gate circuits at 1 volt operation.

We discuss the fabrication of a FLASH EEPROM floating gate memory device with a cell size of 0.0896@mm. The floating gate level utilized an alternating aperture phase shift mask, a binary mask was used to expose the control gate level. Linewidth changes over topography, due to reflectivity variations, was controlled by an inorganic multilayer anti-reflective coating^1. All levels were exposed with a new generation of photoresists developed at Bell Laboratories with ARCH chemicals. Experiments were carried out to give some insight to the behavior of the materials and the viability of optical enhancement techniques. We have found that 193nm lithography with this new family of photoresists is reasonably proficient in the fabrication of devices with design rules of less than half the exposure wavelength.

SCALPEL alignment marks have been fabricated in a SiO 2 /WSi 2 structure using SCALPEL lithography and plasma processing. The positions of the marks were detected through e-beam resist in the SCALPEL proof of lithography (SPOL) tool by scanning the image of the corresponding mask mark over the wafer mark and detecting the backscattered electron signal. Single scans of line space patterns yielded mark positions that were repeatable within 30 nm 3σ with a dose of 0.4 μC/cm 2 and signal-to-noise of 16 dB. An analysis shows that the measured repeatability is consistent with a random noise limited response. The mark detection repeatability limit, that can be attributed to SPOL machine factors, was measured to be 20 nm 3σ. By using a digitally sequenced mark pattern, the capture range of the mark detection was increased to 13 μm while maintaining 36 nm 3σ precision. The SPOL machine mark detection results are very promising considering that they were measured under electron optical conditions that were not optimized.

We report measurements of the Casimir force between a gold sphere and a silicon surface with an array of nanoscale, rectangular corrugations using a micromechanical torsional oscillator. At distance between 150 nm and 500 nm, the measured force shows significant deviations from the pairwise additive formulism, demonstrating the strong dependence of the Casimir force on the shape of the interacting bodies. The observed deviation, however, is smaller than the calculated values for perfectly conducting surfaces, possibly due to the interplay between finite conductivity and geometry effects., Comment: 5 pages, 3 figures

Spatial light modulators (SLMs) designed to replace photomasks for optical lithography have been designed, fabricated, and tested. These microelectromechanical devices are fabricated with alternating polycrystalline Si and sacrificial SiO2 layers that are patterned by a 193nm wavelength scanner to dimensions as small as 150nm. Aerial image simulations were used to define the mechanical requirements of the devices. Piston motion of electrically actuated devices was measured with an optical profilometer. The measurements were fit to a simple equation to within 1nm precision, which is adequate for defining 50nm features lithographically. Transient response measurements show that one version of the SLM responds to actuation as quickly as 20μs, fast enough for current 193nm wavelength excimer laser sources.

The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3–5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintaining reliability. Practical limitations due to direct tunneling through the gate oxide may preclude the use of silicon dioxide as the gate dielectric for thicknesses less than 1.3 nm, however.