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In this paper, a new analysis method is introduced to predict the gap between Shannon limit and successful decoding signal-to-noise ratio threshold (SNR loss) of practical quasi-cyclic low-density parity check (QC-LDPC) codes. The SNR loss of a QC-LDPC code is summed up from three aspects: 1) the base matrix; 2) the number of iterations for decoding; and 3) the finite codeword length. As an example, the SNR loss of DVB-S2 and ATSC 3.0 LDPC codes is analyzed with the proposed method. Results show that a large portion of the SNR loss of DVB-S2 LDPC codes is due to their base matrices, which is significantly improved in latest ATSC 3.0 standard. Furthermore, with the aid of the proposed analysis method, newly designed QC-LDPC codes with raptor-like structure are proposed. Bit-error rate simulations show that the proposed codes are only 0.4 dB away from Shannon limit under binary-input additive white Gaussian noise channel and only 0.65 dB away from Shannon limit under binary-input Rayleigh fading channel, which are comparable with state-of-art design. [ABSTRACT FROM AUTHOR]

Using the Thompson circuit complexity model, it is shown that fully parallel encoding and decoding schemes with asymptotic block error probability that scales as $O(f(n))$ have energy that scales as $\Omega (n{-\ln f(n)}^{1/2})$. In addition, it is shown that the number of clock cycles [ $T(n)$ ] required for any encoding or decoding scheme that reaches this bound must scale as $T(n)\ge {-\ln f(n)}^{1/2}$. Similar scaling results are extended to serialized computation. A similar approach is extended to three dimensions by generalizing the Grover information-friction energy model. Within this model, it is shown that encoding and decoding schemes with probability of block error $P_{\mathrm {e}}(n)$ consume at least $\Omega (n(-\ln P_{\mathrm {e}}(n))^{({1}/{3})})$ energy. [ABSTRACT FROM AUTHOR]

We derive the optimal second-order coding region and moderate deviations constant for successive refinement source coding with a joint excess-distortion probability constraint. We consider two scenarios: 1) a discrete memoryless source (DMS) and arbitrary distortion measures at the decoders and 2) a Gaussian memoryless source (GMS) and quadratic distortion measures at the decoders. For a DMS with arbitrary distortion measures, we prove an achievable second-order coding region, using type covering lemmas by Kanlis and Narayan and by No, Ingber, and Weissman. We prove the converse using the perturbation approach by Gu and Effros. When the DMS is successively refinable, the expressions for the second-order coding region and the moderate deviations constant are simplified and easily computable. For this case, we also obtain new insights on the second-order behavior compared with the scenario where separate excess-distortion proabilities are considered. For example, we describe a DMS, for which the optimal second-order region transitions from being characterizable by a bivariate Gaussian to a univariate Gaussian, as the distortion levels are varied. We then consider a GMS with quadratic distortion measures. To prove the direct part, we make use of the sphere covering theorem by Verger–Gaugry, together with appropriately-defined Gaussian type classes. To prove the converse, we generalize Kostina and Verdú’s one-shot converse bound for point-to-point lossy source coding. We remark that this proof is applicable to general successively refinable sources. In the proofs of the moderate deviations results for both scenarios, we follow a strategy similar to that for the second-order asymptotics and use the moderate deviations principle. [ABSTRACT FROM PUBLISHER]

Polar codes are of great interests because they provably achieve the symmetric capacity of discrete memoryless channels with arbitrary input alphabet sizes while having an explicit construction. Most existing decoding algorithms of polar codes are based on bit-wise hard or soft decisions. In this paper, we propose symbol-decision successive cancellation (SC) and successive cancellation list (SCL) decoders for polar codes, which use symbol-wise hard or soft decisions for higher throughput or better error performance. First, we propose to use a recursive channel combination to calculate symbol-wise channel transition probabilities, which lead to symbol decisions. Our proposed recursive channel combination has lower complexity than simply combining bit-wise channel transition probabilities. The similarity between our proposed method and Arıkan's channel transformations also helps to share hardware resources between calculating bit- and symbol-wise channel transition probabilities. Second, a two-stage list pruning network is proposed to provide a trade-off between the error performance and the complexity of the symbol-decision SCL decoder. Third, since memory is a significant part of SCL decoders, we propose a pre-computation memory-saving technique to reduce memory requirement of an SCL decoder. Finally, to evaluate the throughput advantage of our symbol-decision decoders, we design an architecture based on a semi-parallel successive cancellation list decoder. In this architecture, different symbol sizes, sorting implementations, and message scheduling schemes are considered. Our synthesis results show that in terms of area efficiency, our symbol-decision SCL decoders outperform existing bit-decision and multi-bit SCL decoders. [ABSTRACT FROM PUBLISHER]

Parallel processing and double-flow methods, which are used to increase the speed of turbo-code decoding, cause memory contentions. Although memory contentions due to parallel processing can be resolved by adopting the quadratic polynomial permutation (QPP) interleaver, the double-flow method still causes memory contentions because of its read/write sequences from both ends of the input packets. Thus, we propose a modified architecture to resolve memory contentions for the double-flow method to fit the QPP interleaver. In our experiment, the proposed method has a shorter decoding time and smaller hardware size compared the conventional method. A bit-accurate simulation was performed, and hardware implementation with field-programmable gate arrays (FPGAs) led to a high throughput of 80 Mbps. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [ABSTRACT FROM AUTHOR]

Polar codes have recently received a lot of attention because of their capacity-achieving performance and low encoding and decoding complexity. The performance of the successive cancellation decoder (SCD) of the polar codes highly depends on that of the partial-sum network (PSN) implementation. Hence, in this work, an efficient PSN architecture is proposed, based on the properties of polar codes. First, a new partial-sum updating algorithm and the corresponding PSN architecture are introduced which achieve a delay performance independent of the code length. Moreover, the area complexity is also reduced. Second, for a high-performance and area-efficient semi-parallel SCD implementation, a folded PSN architecture is presented to integrate seamlessly with the folded processing element architecture. This is achieved by using a novel folded decoding schedule. As a result, both the critical path delay and the area (excluding the memory for folding) of the semi-parallel SCD are approximately constant for a large range of code lengths. The proposed designs are implemented in both FPGA and ASIC and compared with the existing designs. Experimental result shows that for polar codes with large code length, the decoding throughput is improved by more than 1.05 times and the area is reduced by as much as 50.4%, compared with the state-of-the-art designs. [ABSTRACT FROM PUBLISHER]

Highlights: [•] We present a framework for the systematic analysis of the decoding delay in MVC. [•] The framework relies on graph theory and decoder model with parallel processing. [•] Iterative algorithm to compute jointly frame processing times and decoding delay. [•] It can be applied to decoder design to minimize the communication latency. [Copyright &y& Elsevier]

Motivated by the importance of hardware implementation in practical turbo decoders, a simplified, yet effective, n-input \max^\ast approximation algorithm is proposed with the aim being its efficient implementation for very low-complexity turbo decoder hardware architectures. The simplification is obtained using an appropriate digital circuit for finding the first two maximum values in a set of n data that embeds the computation of a correction term. Various implementation results show that the proposed architecture is simpler by 30%, on average, than the constant logarithmic-maximum a posteriori (Log-MAP) one, in terms of chip area with the same delay. This comes at the expense of very small performance degradation, in the order of 0.1 dB for up to moderate bit error rates, e.g., 10^-5, assuming binary turbo codes. However, when applying scaling to the extrinsic information, the proposed algorithm achieves almost identical Log-MAP turbo code performance for both binary and double-binary turbo codes, without increasing noticeably the implementation complexity. [ABSTRACT FROM PUBLISHER]

Anovel doping bits based belief propagation decoding algorithm, for rate-adaptive LDPC codes based on fixed bipartite graph code, is proposed. The proposed workmodifies the decoding algorithm, by converting the puncturing nodes to regular source nodes and by following the encoding rule at the decoder. The transmitted doping bits in place of punctured bits, with the modified decoding algorithm at the decoder, feed all the punctured nodes with reliable log likelihood ratios. This enables the proposed decoding algorithm to recover all punctured nodes in the early iteration. The fast convergence leads to decoder complexity reduction while providing considerable improvement in performance. [ABSTRACT FROM AUTHOR]

As improved versions of the successive cancellation (SC) decoding algorithm, the successive cancellation list (SCL) decoding and the successive cancellation stack (SCS) decoding are used to improve the finite-length performance of polar codes. In this paper, unified descriptions of the SC, SCL, and SCS decoding algorithms are given as path search procedures on the code tree of polar codes. Combining the principles of SCL and SCS, a new decoding algorithm called the successive cancellation hybrid (SCH) is proposed. This proposed algorithm can provide a flexible configuration when the time and space complexities are limited. Furthermore, a pruning technique is also proposed to lower the complexity by reducing unnecessary path searching operations. Performance and complexity analysis based on simulations shows that under proper configurations, all the three improved successive cancellation (ISC) decoding algorithms can approach the performance of the maximum likelihood (ML) decoding but with acceptable complexity. With the help of the proposed pruning technique, the time and space complexities of ISC decoders can be significantly reduced and be made very close to those of the SC decoder in the high signal-to-noise ratio regime. [ABSTRACT FROM AUTHOR]

The A* algorithm for decoding linear block codes is known to be an efficient tree-search method for decoding short linear block codes. We propose to employ the early acquired information of some parity bits to speed up the tree search. Analysis for the number of required information bits for obtaining the parity bits is provided. In addition, two versions of the modified A* algorithm which take advantage of the advanced information of parity bits are provided. Simulation results show that there is advantage in reducing the number of search tree edges in each proposed version as compared with two existing A* algorithms which do not consider the early information of parity bits. [ABSTRACT FROM AUTHOR]

Complementary synthesis can automatically synthesize the decoder circuit of an encoder. However, its user needs to manually specify an assertion on some configuration pins to prevent the encoder from reaching the nonworking states. To avoid this tedious task, this paper propose an automatic approach to infer this assertion, by iteratively discovering and removing cases without decoders. To discover all decoders that may exist simultaneously under this assertion, a second algorithm based on functional dependency is proposed to decompose \BBR, the Boolean relation that uniquely determines the encoder's input, into all possible decoders. To help the user select the correct decoder, a third algorithm is proposed to infer each decoder's precondition formula, which represents those cases that lead to this decoder's existence. Experimental results on several complex encoders indicate that our algorithm can always infer assertions and generate decoders for them. Moreover, when multiple decoders exist simultaneously, the user can easily select the correct one by inspecting their precondition formulas. [ABSTRACT FROM AUTHOR]

Maximum likelihood soft-decision decoding of linear block codes is addressed in this correspondence. A novel algorithm based on Chase-2 algorithm for the decoding of systematic binary block codes is detailed. A double re-encoding technique in place of the classical algebraic decoding for the computation of the candidate codeword list is the major innovation of the proposed algorithm. This approach has been successfully applied to systematic block codes that have a code rate equal to 1/2 and a parity check matrix composed of an invertible submatrix for the redundancy part. Simulation results show performance close to the optimum maximum likelihood decoding for an excellent tradeoff between BER performance and computational complexity. Then, the challenging issue of designing a decoder for a specific family of short binary block codes, called Cortex codes is also described. Three soft decoders for Cortex codes with lengths equal to 32, 64, and 128 and a code rate equal to 1/2 have been designed. Then, all the decoders were successively implemented onto an field-programmable gate array (FPGA) device. To our knowledge, they are the first efficient digital implementations of Cortex codes. [ABSTRACT FROM PUBLISHER]

We describe the channel equalization problem, and its prior estimate of the channel state information (CSI), as a joint Bayesian estimation problem to improve each symbol posterior estimates at the input of the channel decoder. Our approach takes into consideration not only the uncertainty due to the noise in the channel, but also the uncertainty in the CSI estimate. However, this solution cannot be computed in linear time, because it depends on all the transmitted symbols. Hence, we also put forward an approximation for each symbol's posterior, using the expectation propagation algorithm, which is optimal from the Kullback–Leibler divergence viewpoint and yields an equalization with a complexity identical to the BCJR algorithm. We also use a graphical model representation of the full posterior, in which the proposed approximation can be readily understood. The proposed posterior estimates are more accurate than those computed using the ML estimate for the CSI. In order to illustrate this point, we measure the error rate at the output of a low-density parity-check decoder, which needs the exact posterior for each symbol to detect the incoming word and it is sensitive to a mismatch in those posterior estimates. For example, for QPSK modulation and a channel with three taps, we can expect gains over 0.5 dB with same computational complexity as the ML receiver. [ABSTRACT FROM AUTHOR]

In this paper, we present an algorithm for joint carrier phase estimation and turbo decoding for the case of rapidly varying carrier phase during the transmitted block. The proposed algorithm shows improved performance over previously proposed communication schemes, both coherent and noncoherent, for channels with additive white Gaussian noise and high carrier phase noise. The novel algorithm utilizes a modified ‘two dimensional’ bit carrier phase a posteriori probability (BCAPP) decoder containing additional states representing the received carrier phase. The BCAPP decoder calculates two extrinsic metrics: one representing the bit soft value and the other representing the received carrier phase probability density function approximation. A modified structure of the turbo code iterations is suggested, implementing separate propagation of the two metrics between the BCAPP decoders. One additional attractive property of the suggested algorithm is its robustness against phase noise model mismatch. [ABSTRACT FROM AUTHOR]

Time-invariant hybrid (HTI) decoding of irregular low-density parity-check (LDPC) codes is studied. Focusing on HTI algorithms with majority-based (MB) binary message-passing constituents, we use density evolution (DE) and finite-length simulation to analyze the performance and the convergence properties of these algorithms over (memoryless) binary symmetric channels. To apply DE, we generalize degree distributions to have the irregularity of both the code and the decoding algorithm embedded in them. A tight upper bound on the threshold of MB HTI algorithms is derived, and it is proven that the asymptotic error probability for these algorithms tends to zero, at least exponentially, with the number of iterations. We devise optimal MB HTI algorithms for irregular LDPC codes, and show that these algorithms outperform Gallager's algorithm A applied to optimized irregular LDPC codes. We also show that compared to switch-type algorithms, such as Gallager's algorithm B, where a comparable improvement is obtained by switching between different MB algorithms, MB HTI algorithms are more robust and can better cope with unknown channel conditions, and thus can be practically more attractive. [ABSTRACT FROM AUTHOR]

Novel simplified merged processing element (SMPE) architectures to design a low-complexity successive-cancellation (SC) polar decoder are presented. The proposed SMPE architectures reduce the number of sign-magnitude conversions and switch networks, relative to those of the conventional merged processing element. Synthesis results show that the (1024, 512) SC polar decoder using the proposed SMPE architectures significantly decreases hardware complexity and improves technology scaled normalised throughput, as compared to those of the previously reported architectures. [ABSTRACT FROM AUTHOR]

A new architecture for a polar decoder using a reduced complexity successive-cancellation (SC) decoding algorithm is presented. This novel fully unrolled, deeply pipelined architecture is capable of achieving a coded throughput of over 237 Gbit/s for a (1024, 512) polar code implemented using a field-programmable gate array. This decoder is two orders of magnitude faster than state-of-the-art polar decoders. [ABSTRACT FROM AUTHOR]

A polar coding method to construct a distributed source coding scheme which can achieve any point on the dominant face of the Slepian-Wolf rate region for sources with uniform marginals is proposed. Source encoding and decoding operations are performed using efficient algorithms which makes practical implementation feasible. Simulation results are given to exhibit the performance of the presented method. [ABSTRACT FROM AUTHOR]

A latency reduced method is proposed based on the modified successive cancellation (MSC) decoder for decoding polar codes. In the MSC decoder, it was shown that latencies for both the rate-zero and the rate-one nodes can be reduced. By redistributing the information bits, the proposed method can obtain a good rate-zero and rate-one nodes distribution, in which decoding latency can be further reduced under the MSC decoder. Simulation results show that the new polar code (obtained by the proposed method) achieves 8.5% latency reduction with neglected error performance loss compared with the original polar code. Furthermore, it is easy to adjust the trade-off between the error performance and decoding latency by the proposed method. [ABSTRACT FROM AUTHOR]