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A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested codes. Unlike other previous GDBF algorithms that provide an escape from local maxima, the proposed algorithm uses only local, fully parallelizable operations and does not require computing a global objective function or a sort over symbol metrics, making it highly efficient in comparison. The proposed NGDBF algorithm requires channel state information which must be obtained from a signal to noise ratio (SNR) estimator. Architectural details are presented for implementing the NGDBF algorithm. Complexity analysis and optimizations are also discussed. [ABSTRACT FROM AUTHOR]

Techniques are evaluated for implementing error correction codes in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-VT analog decoding techniques. Novel sub-VT digital designs are proposed, and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub-VT implementation is predicted to offer 29\times gain in power consumption for a (3,6) low-density parity-check decoder of length N = 512 operating at a throughput of 200 Mb/s, compared to standard digital implementation of the same design. [ABSTRACT FROM AUTHOR]

Stochastic decoding is a recently proposed approach for graph-based iterative error control decoding. We present and investigate three hysteresis methods for stochastic decoding on graphs with cycles and show their close relationship with the successive relaxation method. Implementation results demonstrate the tradeoff in bit error rate performance with circuit complexity. [ABSTRACT FROM PUBLISHER]