Search

Promising interconnect materials continue to emerge and are considered as potential replacements for Cu interconnects. In this article, an interconnect technology/system codesign methodology is presented to efficiently optimize generic interconnects using ballistic materials. The key requirements of material-level characteristics to replace conventional Cu counterparts are quantified, such as the channel density, mean free path (MFP), and contact resistance. Furthermore, to achieve maximal chip-level throughput, two interconnect design schemes are proposed and optimized under a given number of metal layers, die area, and power density constraints. Results demonstrate that the optimal design scheme strongly depends on the power constraint, driving devices as well as material parameters, including the contact resistance. It is shown that up to 45% of the throughput improvement can be achieved by replacing both local and intermediate Cu interconnects at an ultralow-power budget. [ABSTRACT FROM AUTHOR]

As the traditional CMOS technology encounters significant scaling challenges, many emerging beyond-CMOS devices have been proposed and developed to augment or even replace CMOS devices. Spintronic devices have received extensive attention due to several unique attributes, including a low operation voltage and nonvolatility. However, spintronic devices are intrinsically slow because of the long switching delay of the magnet. To overcome the drawback, in this article, we propose and develop a deep pipeline method for generic spintronic majority-gate-based circuits. A fast and efficient pipeline buffer insertion methodology is integrated into the industry-standard placement and routing design flow to ensure the correct functionality. The proposed framework can accurately capture 1) the timing of a multiphase clock-gated spintronic circuit and 2) the energy overhead associated with the supply clocking, which is one major overhead of spintronic circuits. Based on the proposed framework, we demonstrate that a spintronic circuit implemented with a deep pipeline can provide over $10\times $ reduction in energy-delay products compared to their traditional CMOS-based counterparts. In the case study, the proposed deep pipeline method is applied to three emerging spintronic devices. Results show that device-level parameters have significant impacts on circuit-level performance and optimal logic depth. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

This letter presents a uniform interconnect-centric benchmark methodology for various emerging charge-based device technologies, including ferroelectric FETs, tunneling FETs, piezoelectric FET, graphene pn junction, and 2D material-based FET. Multiple key metrics are proposed and implemented to quantify the circuit/system limitations imposed by repeaters and interconnects. The results in this letter give device technologists an insightful perspective to better balance and manage the trade-offs of intrinsic device properties for the optimum interconnect performance. [ABSTRACT FROM AUTHOR]

This paper analyzes the impact of the interconnect variation at the system level in terms of clock frequency based on a fast and efficient system-level variation-aware design methodology. Various types of interconnect variations are compared, such as the critical dimension for line/core and spacer, etch, chemical mechanical polishing (CMP), and overlay variations. The $3 \sigma $ values for these independent variation values are extracted from various fabrication processes, including the litho-etch-litho-etch (LELE) double patterning, self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP). The results indicate that the impact of the interconnect variation on the clock frequency increases for a processor at a smaller technology node, especially for the CMP variation. For the impact of the combination of five sources of interconnect variations, the processor using the SADP performs the best. The overlay variation and the spacer variation have a larger impact on the LELE double patterning and the SAQP patterning techniques. Up to 8% and 16% of the frequency drops are observed based on $1\times $ and $2\times $ of the default $3 \sigma $ values, respectively. [ABSTRACT FROM PUBLISHER]

Based on realistic circuit- and system-level simulations, graphene interconnects are analyzed in terms of multiple material properties, such as the mean free path (MFP), the contact resistance, and the edge roughness. The benchmarking results indicate that the advantage of using graphene interconnects occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay product (EDP). At the circuit level, one representative circuit, a 32-bit adder, is investigated, where up to 40% and 70% improvements in delay and EDP are observed. At the system-level analysis, an ARM Cortex-M0 processor is synthesized, and placement and routing are performed. After replacing copper interconnects with multilayer graphene interconnects, up to 15% and 22% performance improvements in clock frequency and EDP have been observed. It is also demonstrated that the benefits of using graphene for the ARM core processor are strongly dependent on the quality of the graphene, such as the MFP and the edge roughness. [ABSTRACT FROM AUTHOR]

As the technology scales down to the sub-10 nm nodes, the interconnect performance becomes primarily dominated by the resistance rather than the capacitance due to the ever-increasing size effects of copper and a higher input capacitance of the devices. The implications of this paradigm shift are discussed in this letter, and it is shown that the local interconnect technology needs to be reoptimized to rebalance the interconnect resistance and capacitance. One approach is to increase the interconnect width beyond half pitch without changing the interconnect pitch. For the 5-nm technology node with an aspect ratio of 3, the energy-delay product of vertical field-effect transistor circuits at the optimal relative width improve up 55%, compared with the circuits using an aspect ratio of 2 and an interconnect width of half pitch. [ABSTRACT FROM AUTHOR]

In the above-named paper [ibid., vol. 37, no. 4, pp. 508?511, Apr. 2016], a typo was found in equation 3. The corrected equation is provided. [ABSTRACT FROM AUTHOR]