1. A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s.
- Author
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AlMarashli, Ahmad, Anders, Jens, Becker, Joachim, and Ortmanns, Maurits
- Subjects
DIGITAL-to-analog converters ,COMPUTER storage devices ,DELTA-sigma modulation - Abstract
This paper introduces an architecture and design for high-resolution high-linearity Nyquist rate successive approximation register (SAR) analog-to-digital converters (ADCs) using a hybrid capacitive and incremental $\Sigma \Delta $ digital-to-analog converter (DAC). The proposed architecture benefits from an intrinsically linear 1.5-bit $\Sigma \Delta $ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC (CDAC). The achieved linearity relies neither on a highly matched CDAC nor on any dynamic linearization techniques but on a single calibration of the coarse CDAC using the available $\Sigma \Delta $ DAC at startup. Therefore, the CDAC can be sized solely upon noise requirements. The SAR ADC employs two parallel dynamic comparators for improved power efficiency. A prototype was fabricated in a 40-nm CMOS, with power supplies of 1.1 and 2.5 V. It occupies an active area of only 0.074 mm2. The prototype achieves a measured peak spurious free dynamic range (SFDR) of 107 dB and peak signal to noise and distortion ratio (SNDR) of 84.8 dB dB at 80-kS/s Nyquist rate operation with 5.3-kHz input. The measured performance at the Nyquist frequency, limited by signal source quality, is SFDR = 99.5 dB and SNDR = 83.5 dB. The core power consumption is 110 $\mu \text{W}$. In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5-kHz bandwidth. [ABSTRACT FROM AUTHOR]
- Published
- 2018
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