Search

This paper introduces an architecture and design for high-resolution high-linearity Nyquist rate successive approximation register (SAR) analog-to-digital converters (ADCs) using a hybrid capacitive and incremental $\Sigma \Delta $ digital-to-analog converter (DAC). The proposed architecture benefits from an intrinsically linear 1.5-bit $\Sigma \Delta $ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC (CDAC). The achieved linearity relies neither on a highly matched CDAC nor on any dynamic linearization techniques but on a single calibration of the coarse CDAC using the available $\Sigma \Delta $ DAC at startup. Therefore, the CDAC can be sized solely upon noise requirements. The SAR ADC employs two parallel dynamic comparators for improved power efficiency. A prototype was fabricated in a 40-nm CMOS, with power supplies of 1.1 and 2.5 V. It occupies an active area of only 0.074 mm2. The prototype achieves a measured peak spurious free dynamic range (SFDR) of 107 dB and peak signal to noise and distortion ratio (SNDR) of 84.8 dB dB at 80-kS/s Nyquist rate operation with 5.3-kHz input. The measured performance at the Nyquist frequency, limited by signal source quality, is SFDR = 99.5 dB and SNDR = 83.5 dB. The core power consumption is 110 $\mu \text{W}$. In oversampling mode, the ADC achieves an SNDR above 90 dB over a 5-kHz bandwidth. [ABSTRACT FROM AUTHOR]

This paper presents a continuous-time third-order low-pass delta-sigma modulator (DSM) with digitally enhanced out-of-band (OOB) signal filtering for enhanced blocker rejection in receiver analog-to-digital converters (ADCs). It is well known that strong OOB interferers define the required dynamic range (DR) of a receiver. Usually, a channel-select filter (CSF) is therefore required, together with the succeeding ADC. The feedback-compensated DSM can relax the CSF with its signal transfer characteristic. In this work, this is improved with a reconfigurable digital filter, which modifies the feedback signal of the outer-loop DAC to increase the OOB blocker rejection of the modulator. As a proof of concept, the digitally improved blocker rejection is shown in a prototype design. Additionally, a reconfigurable excess loop delay compensation technique based on an adaptive delay-locked-loop (DLL) has been implemented. The prototype is realized in a 90 nm CMOS technology, works at 480 MHz clock frequency, requires an area of 0.17\;\textmm^2, and achieves an in-band (IB) SNDR of 70 dB in a bandwidth of 10 MHz with a power consumption less than 14.4 mW. In the prototype, a digitally reconfigurable blocker rejection is realized achieving 6 dB additional suppression from 20 or 40 MHz on, or even 25 dB at the specific frequency of 20 MHz. [ABSTRACT FROM PUBLISHER]

This paper presents a single loop, third order continuous time ΔΣ modulator with an internal 4 bit quantizer sampled at 500 MHz with only an oversampling ratio of 10. Since multi-bit operation commonly suffers from DAC non-linearities, and dynamic element matching is ineffective at low oversampling, an alternative auxiliary DAC linearization is proposed for ΔΣ modulators. The unit element mismatches are digitally estimated based on a cross correlation of a binary test signal with the modulator output and represent the measured DNL of DAC1. The corresponding INL is calculated and stored in an 15×8 lookup-table which is applied to the 8 bit auxiliary DAC to linearize DAC1. Moreover, a design centering approach for amplifier finite gain bandwidth compensation within the loop filter is presented which allows for large bandwidth mismatch with negligible effect on loop filter stability. This results in a robust architecture over temperature, supply, and excess loop delay variations. The presented ΔΣ modulator achieves an SNDR of 67.5 dB, DR of 72 dB, and SFDR of 79 dB over a 25 MHz bandwidth and is implemented in a 1.2 V, 90 nm CMOS process. The modulator occupies an active area of 0.19 mm² and has a power consumption of 8.5 mW. It achieves a figure of merit of 88 fJ/conv-step which is one of the best published for multi-bit ΔΣ modulators. [ABSTRACT FROM PUBLISHER]

In this brief, a hardware-accelerated simulation environment for continuous-time (CT) \Sigma\Delta modulators is presented. Due to the presence of the nonlinear quantizer, simulating \Sigma\Delta modulators is a complicated task in general. The simulation of CT modulators is even more time consuming than that of their discrete-time counterparts, due to the analog loop filter. In particular, in an automated design environment, a large number of simulations have to be performed during the design process of \Sigma\Delta modulators. In this brief, it is shown for the first time that the system-level emulation of CT \Sigma\Delta modulators on an field-programmable gate array results in a significant acceleration, reducing the simulation time by a factor of more than \10^5 compared to a commonly used Simulink simulation. This allows simulating 10 000 of modulators per second, enabling the use of heuristic search algorithms for real-time design for CT \Sigma\Delta modulators. [ABSTRACT FROM AUTHOR]

This brief presents a background digital-to-analog converter (DAC) error estimation technique for multibit bandpass Delta–Sigma analog-to-digital converters (\Delta\Sigma ADCs). The technique is used to estimate and linearize the intrinsic mismatches of feedback DAC unit elements of \Delta\Sigma ADCs. It consists of three building blocks, namely, a correlation-based error estimation, which utilizes a test signal to estimate DAC unit element gain mismatches; a digital error correction, which corrects the estimated DAC nonlinearities; and a unit establishing background operation. The method has been successfully utilized for lowpass \Delta\Sigma ADCs and is extended here by using an additional bandpass filter to create a modified test signal, which meets the requirements of bandpass \Delta\Sigma modulators. The method restores highly nonlinear systems back to their ideal linearity while requiring only little additional hardware effort and enables the design of linear multibit bandpass \Delta\Sigma modulators. [ABSTRACT FROM PUBLISHER]

This paper presents a third order, single-loop, continuous-time \Delta \Sigma modulator with an internal 4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of only 10. Therefore, DAC linearization by dynamic element matching is ineffective, and the DAC nonlinearities are not corrected within the \Delta \Sigma modulator loop but in the subsequent digital circuit. The unit element mismatches are digitally estimated based on a correlation, and correction factors are thus derived. Moreover, in order to achieve a low-power operation, all amplifiers are compensated for finite gain-bandwidth related non-idealities. In the presented work, this compensation includes the fast proportional loop, which is used to compensate for excess loop delay. The presented \Delta \Sigma modulator has been realized in a 1.2 V, 90 nm CMOS process and achieves an SNDR of 63.5 dB and an SFDR of 81 dB within a 25 MHz bandwidth. The modulator occupies an active die area of only 0.15 \mm^2 and has a power consumption of 8 mW, with an additional 0.02 \mm^2 and 0.42 mW estimated for the digital DAC correction logic. The overall modulator achieves a figure of merit of 138 fJ/conv. [ABSTRACT FROM AUTHOR]