Search

In this letter, the dynamic Ron degradation mechanisms of the p-GaN gate HEMTs induced by off-state stress are investigated with different passivation dielectrics AlON and SiN. The degradation mechanisms are twofold, including VTH shift and surface trapping in the gate-to-drain access region, whose impacts are successfully distinguished. Surface trapping by SiN passivation is evidently proved to be the dominant factor that can almost induce a full current collapse. The VTH positive shift diminishes the drain current by shrinking the overdrive VGS, which however, can be compensated by a higher VGS overdrive in applications. SiN passivation can effectively suppress the positive bias temperature instability effect, probably by passivating the p-GaN fast traps with hydrogen during passivation. Last, the transient measurements unveil that both the surface trapping and VTH shift have a very slow recovery process. [ABSTRACT FROM AUTHOR]

Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because of the absence of short-channel effects and of a subthreshold-slope limit. As a solution to the low on-currents of silicon-based TFETs, the incorporation of silicon-germanium at the source-channel interface has been considered. However, the understanding of the band-to-band-tunneling mechanism at heterojunctions is incomplete. We have investigated through device simulations and modeling the impact of source-material modifications on the tunnel current in n-channel nanowire TFETs. Our modeling work includes the development of a semi-analytical model, which determines the tunnel probability along the dominant tunnel path in two-dimensional TFETs. In particular, we have analyzed the impact of the bandgap, electron affinity, effective mass, dielectric constant, and density of states of both source and channel material. We show that a small-bandgap source material and a large positive electron-affinity offset at the source-channel interface boost the tunnel current of n-channel TFETs. [ABSTRACT FROM AUTHOR]

We investigated plasma treatment induced water absorption in a SiOCH low-k dielectric and the influence of the absorbed water components on the low-k dielectric reliability. By using thermal desorption spectroscopy (TDS), water absorption in SiOCH was evidenced for N2/H2 plasma treatments. Based on these TDS results, two anneal temperatures were selected to separate and quantify the respective contributions of two absorbed water components, physisorbed (α) and chemisorbed (β) water, to low-k dielectric reliability. With the physisorbed water desorbed by an anneal at 190 °C, the low-k dielectric shows reduced leakage currents and slightly improved time-dependent dielectric breakdown (TDDB) lifetimes. However, the observed failure mechanism represented by the TDDB thermal activation energy (Ea) does not change until the chemisorbed water component was desorbed by an anneal at 400 °C. The close similarity between Ea and the bond energy associated with the β water component demonstrates that the β bond is among the weakest links for the SiOCH low-k dielectric breakdown. [ABSTRACT FROM AUTHOR]

In this work, we employ the substrate hot electron injection technique as a characterization tool to examine the defect creation mechanisms in high-k HfSiON gate stacks, taking advantage of the independent control over oxide field, electron fluence, and injected electron energy which the technique allows. We show that defect creation and oxide breakdown are dependent on the energy of the injected electrons and not on the oxide field. Furthermore, we show that the energy of the injected electrons governs whether the majority of the defects are created at the Si/SiO2 interface or in the bulk of the material. Results show that at operating conditions, the primary threat to device reliability from hot carrier damage is the introduction of a permanent 3D positive bias temperature instability component introduced by increased interface trap generation, even for carriers with energy slightly above that of field accelerated electrons. We also discuss the feasibility of using substrate hot electron injection as a means to accelerate time dependent dielectric breakdown measurements, thereby allowing degradation at lower oxide fields to be probed. [ABSTRACT FROM AUTHOR]

The charge trapping is studied in metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with SrBi2Ta2O9 (SBT)/Al2O3/SiO2 gate stack by high-frequency and pulsed capacitance-voltage (CV) measurements. The ferroelectric polarization is observed by high-frequency CV. Under fast gate voltage sweep in pulsed CV, the delay of electron trapping detrapping in the buffer layer induces an opposite CV hysteresis direction than that of the ferroelectric polarization. For memory programming, the hole trapping in the gate stack limits the electric field in SBT. Furthermore, the electron trapping during stress induces serious threshold voltage instability as well as erratic memory read out. All these charge trapping problems are important for the practical application and reliability of the memory with MFIS structure. [ABSTRACT FROM AUTHOR]

We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low- $k$ damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu damascene wires, integrated with a Ru-based liner, currently investigated for the 7 nm logic technology node. The capacitance is simulated by means of a 2D field solver (Raphael) by Synopsys. The impact of line dimensions is analyzed for the case of 32 nm pitch interconnects, which are representative of the 7 nm logic technology node. We show that for aspect ratios greater than 1, the resistance is more sensitive to variations of the line width rather than of the line height, because of the higher surface scattering induced by the sidewall interfaces, which are closer to each other compared with the top and bottom interfaces. For capacitance, low- $k$ sidewall damage exacerbates capacitance sensitivity to line dimensions and, for typical interconnect schemes, the impact of line width variations dominates over variations of the line height. We demonstrate that for a given pitch and dielectric stack height, the RC delay can be significantly reduced by targeting wider and deeper damascene trenches, that is, by trading capacitance for resistance, and that an optimal wire geometry for RC delay minimization exists. In addition, we show that a given RC delay can be achieved with several geometries and, therefore, $R$ and $C$ pairs, which represents a useful degree of freedom for designers to optimize system-level performance. As an application, we analyze a possible 7 nm technology scenario and show that wide and deep damascene trenches can mitigate the impact of the increased wire resistance on circuit delay. [ABSTRACT FROM AUTHOR]

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al2O3 gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxation. Hence, a defect band model with different distributions of defect levels inside the gate dielectric is proposed, which can excellently reproduce the experimental data and provide insightful information about the origin of PBTI in GaN MISFETs. The results indicate that the serious PBTI in the device with PEALD SiN is mainly due to a wide distribution of defect levels ( \sigma \sim 0.67 eV), centered below the conduction band of GaN ( E_{C} -0.05 eV), and can be easily accessed by the channel carriers already at a low-gate voltage. On the other hand, ALD Al2O3 gate dielectric shows a narrower distribution of defects ( \sigma \sim 0.42$ eV), which are far from the conduction band of GaN ( E_{C} +1.15 eV). This observations explain the improved PBTI reliability observed in devices with ALD Al2O3. [ABSTRACT FROM AUTHOR]

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si-pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO2/Al2O3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the time exponent varies with stress biases/field when measured by either the conventional slow dc or pulse I-V technique, making the conventional Vg -accelerated method for predicting the lifetime of Si-pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO2/Al2O3 can be fully annealed at 150 ^\circC ; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., Ev , when neutral, lift well above Ev after charging, and return below Ev following neutralization. [ABSTRACT FROM PUBLISHER]

Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a \SiO2/ \HfO2 dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups. [ABSTRACT FROM PUBLISHER]

The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H^+ species released from the Si/SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H^+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs. [ABSTRACT FROM PUBLISHER]

Trap-assisted tunneling (TAT) is a major hurdle in achieving a sub-60-mV/decade subthreshold swing (SS) in tunnel field-effect transistors (TFETs). This paper presents an insight into the TAT process in the presence of field-induced quantum confinement (FIQC) in line TFETs. We show that the SS degradation in line TFETs is mainly caused by TAT through traps located in the bulk of the semiconductor nearby the gate dielectric. For an Si n-type TFET, the energy quantization in the conduction band is found to suppress the TAT through the interface-region traps by several orders of magnitude and delay the TAT through bulk traps nearby the gate dielectric with several hundreds of millivolts. The trap levels closer to the conduction band were found to be the most efficient for TAT in this n-TFET. The FIQC onset voltage shift in TAT through bulk taps is found to be smaller than the band-to-band tunneling (BTBT) shift, enhancing the effective SS degradation in TFETs. We therefore show that it is equally important to include the FIQC effect when calculating TAT as when calculating BTBT generation rates. [ABSTRACT FROM PUBLISHER]

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of \Si/SiO2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI. [ABSTRACT FROM AUTHOR]

The underlying physical mechanism of the Vth adjustment of nMOSFETs with HfSiO/TiN gate stack obtained by As and Ar implantation is investigated. It is experimentally proved that the trapped charge in the HfSiO bulk defects controls the initial Vth value in nMOSFETs. The reduction of the charged trap density in HfSiO by implant explains the tuned Vth values. [ABSTRACT FROM PUBLISHER]

A methodology to incorporate the MOSFET gate dielectric breakdown (BD) failure mechanism in the design of complex systems is presented. The model accounts for the statistical nature of the BD phenomenon, is easily extensible to different device geometries and operation conditions (following the established scaling rules for the mechanism), considers the stress history, and can be easily implemented in circuit simulation tools. Device level characterization of the BD mechanism is presented, which is the base for model parameter extraction. The model has been introduced in a circuit simulator to show its suitability for evaluation of the BD effect in circuits and their reliability, taking ring oscillators as example. [ABSTRACT FROM PUBLISHER]

Interface states play an important role in the performance of MOSFETs, and previous works only addressed the states within band gap. The implicit assumption is that the states beyond band gap (SBBs) are negligible, but there is no experimental evidence supporting it. Because of a lack of techniques for characterizing SBBs, there is hardly any information available. The central objective of this paper is to develop a technique for evaluating SBBs and to show the impact of SBBs on mobility evaluation. For the first time, the pulse capacitance–voltage has been used to extract SBBs quantitatively. It is found that SBBs can reach the order of \10^13 \ \cm^-2\cdot\eV^-1 beyond both conduction- and valence-band edges on a fresh MOSFET. The conventional split C– V technique ignores the SBBs, and this can lead to an underestimation of carrier mobility over 30%. Using the newly developed technique as a tool, the impact of nitridation of Hf-based dielectric stacks on carrier mobility is assessed. As nitrogen density increases, the apparent reduction of carrier mobility observed by early works originates from the higher SBBs. Once SBBs are taken into account, nitridation does not degrade carrier mobility. The SBBs are sensitive to process conditions, and this paper opens the way for their minimization. [ABSTRACT FROM AUTHOR]

A time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed. The structure, validity, and accuracy of the model are evaluated and discussed. The model is applied to an interconnect scaling scenario that includes conventional patterning and spacer-defined patterning of nanometer-scale Cu wires. LER-aware TDDB lifetime predictions are obtained from the model, and consequent recommendations on how to improve the TDDB lifetime of future interconnects are derived. [ABSTRACT FROM PUBLISHER]

Characterizing interface states is a key task, and it typically takes seconds when conventional techniques, such as charge pumping (CP), are used. The stress-induced degradation can recover substantially during this time, and there is a need to improve the measurement speed. The central task of this work is to reduce the measurement time for interface states from seconds to microseconds to minimize the recovery. A fast single pulse CP (SPCP) technique is developed. By exploring the differences in the transient currents corresponding to the two edges of the gate pulse, the net charges pumped into devices can be obtained, and their saturation level is used to evaluate interface states. Unlike the conventional CP (CCP) method, the contribution of currents during the plateaus of gate pulse is excluded for SPCP, making it less vulnerable to the interferences of gate leakage and defects within dielectrics. For the first time, the SPCP allows the recovery of interface states being monitored with a time resolution in microseconds. The results show that the recovery of stress-induced interface states is substantial within 100 \mu\s, which would be missed if the CCP were used. [ABSTRACT FROM PUBLISHER]

In ultrascaled complimentary metal–oxide–semiconductor technologies, the lucky-electron model does not describe correctly Channel Hot-Carrier (CHC) degradation for typical transistor test conditions independently of the gate dielectric (\SiO2 or high- k). A new model to describe the CHC degradation behavior in n-channel metal–oxide field-effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented. This new model can be applicable to long- and short-channel transistors with high- k or \SiO2 as a dielectric. [ABSTRACT FROM PUBLISHER]

A fast response technique is developed to investigate the short-term postprogram and post-erase discharge in Flash memory devices. The procedure is based on fast VTH -evaluation methods developed for bias temperature instability and provides the transient characteristics after 20 ms under the program or erase conditions. The following different structures are investigated: 1) \SiO2/high-k stacks; 2) charge trap memories; 3) and floating gate memories. Dielectrics targeted for Flash memory applications are used as charge trap layers and interpoly dielectrics. In this paper, we show results on \Al2\O3, DyScO, GdScO, and hexagonal and perovskite LuAlO. The postprogram and post-erase curves hold useful information about the dielectric properties and are used as a fast screening technique for alternative materials. [ABSTRACT FROM PUBLISHER]

Predicting negative bias temperature instability (NBTI) lifetime can be dangerous since it is difficult to assess its safety margin. The common technique uses gate bias Vg acceleration to reduce the test time, and the data were typically obtained from quasi-dc measurements. Recently, it has been shown that substantial recovery occurs during the quasi-dc measurement, and the suppression of recovery requires using ultrafast pulse measurement, where time was reduced to the order of microseconds. In a real circuit, different transistors have different levels of recovery, and the worst case scenario is when recovery is suppressed. At present, there is little information on how this worst case NBTI lifetime can be predicted and whether the traditional Vg acceleration technique can still be used. This work will show that the prediction based on the Vg acceleration results in a substantial error, and its cause will be analyzed. To predict the worst case lifetime, a model for NBTI kinetics under operation gate bias is developed. This kinetics includes contributions from both as-grown and generated defects, and it no longer follows a simple power law. Based on the new kinetics, a single-test prediction method is proposed, and its safety margin is estimated to be 50%. [ABSTRACT FROM AUTHOR]

One of the fundamental questions for gate-stack scaling is whether the low-field mobility measured in long-channel devices is a good proxy for short-channel performance at high field. In this paper, we thoroughly investigate low- and high-field transports (velocity and mobility) in 1-nm-EOT high-κ materials on Si (100) and (110) down to cryogenic temperature. It is shown that scattering in Si substrate dominates the transport at high field, thus enabling relaxation of the low-field-mobility requirement for future scaling below 1-nm EOT. [ABSTRACT FROM AUTHOR]

In this paper, we study time-dependent dielectric breakdown in thin gate oxides and propose a new methodology applicable to a wide range of gate stacks for extracting breakdown (SBD) and post-SBD wear-out (WO) parameters measuring the time to hard breakdown (tHBD) only. By introducing this methodology, we can get around the problems related to the detection of the first SBD and the corresponding WO time. We show that the shape of the HBD distribution can change with voltage and area, depending on the ratio of WO and SBD times. We also explain why, in literature, contradictory results related to the voltage acceleration factors of SBD and WO are reported. Finally, we construct a complete reliability prediction model includes SBD and WO. [ABSTRACT FROM AUTHOR]

This paper shows important improvements in charge pumping (CP) measurements on stacked high-k dielectrics, where the defects in high-k and SiO2 can be distinguished and estimated. The spatial profile of the interface traps and bulk traps is obtained by plotting the trap density as a function of the discharge time. Furthermore, the spectroscopic character of the base-level CP technique is demonstrated in HfSiON/SiO2 gate dielectrics by changing the applied pulse bias. It is found that when large pulse amplitude is applied to the gate, two bands appear superimposed on top of the usual base-level CP curve, suggesting the presence of two separate defect energy levels in the high-k dielectric. [ABSTRACT FROM AUTHOR]

A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability ΔVth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates ΔVth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of ΔVth is clarified. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) with HfCl4 as a precursor is widely used for HfO2 fabrication. Due to the nature of the precursor under study, i.e., HfCl4 and H2O, the presence of chlorine residues in the film due to insufficient hydrolysis is eminent. Obviously, the chlorine residue in the HfO2 film is suspected to affect the quality of the HfO2 film. In this paper, we reduced the concentration of chlorine residues by increasing the H2O oxidant pulse time in between the deposition cycles from 0.3 to 10 and 90s. Time-of-flight secondary ion mass spectrometry analysis shows that this decreases the chlorine concentration in the HfO2 film by more than one order of magnitude. However, time-dependent dielectric breakdown analysis shows that the lifetime remains quasi unaffected (within identical error bars) for the different injection cycles. Charge pumping analysis was done by varying both pulse frequency and amplitude to investigate the creation of defects, but negligible differences were observed. Therefore, we conclude that the presence of chlorine residues has no significant impact on the trap generation and reliability of ALD HfO2 layers, and this result corresponded with the mobility result. The experimental picture is confirmed with first-principle calculations that show that the presence of chlorine residues does not induce defect levels in the bandgap of HfO2. [ABSTRACT FROM AUTHOR]

The effects of source/drain activation thermal bud- get and premetallization degas conditions on interfacial re- growth, carrier mobility, and defect densities are examined for SiO2/HfO2/TaN stacks. We observe a correlation between the mobility degradation and the interfacial re-growth possible with the thermal budget employed. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-κ bulk, as detected by both pulsed current-voltage and charge-pumping measurements. Two junction activation processes have been applied: a conventional process (peak temperature of 1000 °C spike for t = 1 s) and a Solid Phase Epitaxial Re-growth (SPER) (peak temperature of 650 °C for t = 60 s). For 1000 °C spike-annealed films, where the highest SiO2/IL defect density is observed, the consequent mobility degradation is explained by a transition region between HfO2 and the IL which increases for high-temperature processing. [ABSTRACT FROM AUTHOR]

In this paper, complementary measurements of the drain and the gate low-frequency noise are used as a powerful probe for sensing the hafnium-related defects in nMOSFETs with high-k gate stacks and polysilicon gate electrode. Drain noise measurements indicate that for low hafnium content (23%) and thin high-k thickness (2 nm), the defect density at the substrate/dielectrics interface is similar to the case of conventional SiO2. Gate-noise measurements suggest that the defect density in the bulk of the high-k gate stacks and at the gate/dielectrics interface is strongly degraded by the hafnium content. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new methodology for sensing the breakdown location along the channel length with the MOSFET biased in the inversion regime. The usefulness of this technique is demonstrated in the characterization of ultrathin Hf-silicate gate dielectrics breakdown. Two different breakdown modes are deconvoluted: an initial progressive breakdown in the channel with a degradation rate strongly dependent on the applied voltage and a successive hard-breakdown at source and drain extensions, which more impacts the device reliability. [ABSTRACT FROM AUTHOR]

Dielectric relaxation currents in SiO2 /Al2O3 and SiO2 /HfO2 high-κ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-κ dielectric stacks. It is found that high-κ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-κ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO2/high-κ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO2/high-κ interface is a key requirement for high-κ dielectric stack application and reliability in MOS devices. [ABSTRACT FROM AUTHOR]

Based on the so-called defect-centric statistics, we propose the average impact of a single charged trap on FET threshold voltage as a physically based measure of the random component of time-dependent variability. We show that it can be extracted using matched pairs, analogously to time-zero variability. To that end, the defect-centric statistics of matched pairs are discussed and the correlation between time-zero and time-dependent variances is formalized. [ABSTRACT FROM AUTHOR]

The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO2 and HfO2 dielectrics with metal gate is investigated. The threshold voltage shift (\DeltaVTH) at identical NBTI over-drive stress conditions is observed to be lower in ZrO2 than in HfO2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation (\DeltaNit) in the sub-1-nanometer EOT devices, with ZrO2 devices showing about one order of magnitude lower \DeltaNit than HfO2 device. However, the \DeltaNit contribution to the total \DeltaVTH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id–Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO2, which decisively reduces NBTI in ZrO2 gate dielectric. [ABSTRACT FROM PUBLISHER]

A study of the negative and positive bias temperature instability (N/PBTI) reliability of FinFETs with different TiN metal gates deposited by either atomic layer deposition (ALD) or physical vapor deposition (PVD) on \HfO2 dielectrics found that the nonuniformity of the interfacial oxide layer is closely related to reliability characteristics. FinFETs with an ALD TiN gate exhibit better NBTI and PBTI lifetimes than those with a PVD TiN gate. In addition, the dependence of fin width on NBTI reliability appeared to be worse with narrower fins, whereas PBTI reliability improves. [ABSTRACT FROM PUBLISHER]

In this letter, submelt laser anneal used to achieve ultrashallow junctions (USJs) in capped high-k devices with TaN/ TiN metal gate electrode is investigated. The submelt laser anneal results in USJ and sharp junction on both n- and pMOSFET devices. However, this process induces interface and bulk defects and reduces negative-bias temperature instability (NBTI) reliability additionally. It is shown that if the laser anneal is followed by a rapid thermal anneal, the laser-related damage decreases, and the NBTI robustness improves without altering the obtained junction sharpness. [ABSTRACT FROM AUTHOR]

We focus on slow de-trapping phenomena in AlGaN/GaN MIS-HEMTs with a bilayer dielectric ( in-situ Si 3 N 4 /Al 2 O 3 ) with two different thicknesses of in-situ Si 3 N 4 (10 nm and 5 nm). By using a “filling pulse” at a positive gate voltage, a trap with activation energy of 0.69–0.7 eV was identified to be responsible for the V TH shift. Based on literature, filling conditions, and the simulated band diagrams, this trap is most probably located at the interface between the dielectrics and AlGaN barrier. A physical model is proposed to explain the V TH shift due to the trapping/de-trapping phenomena based on the occupation dynamics of donor traps at the interface between the in-situ Si 3 N 4 /Al 2 O 3 and the AlGaN barrier. [ABSTRACT FROM AUTHOR]

Abstract: In order to reduce the gate leakage current, high-k gate dielectrics are expected to replace SiO2 in future CMOS generations. Many of these novel dielectrics are stacks of a thin SiO2 and a high-k layer. We present a theoretical study that aims at identifying the combination of the stack architecture and high-k material with the lowest leakage current. In the first part of this work the leakage current through high-k double stacks with various thicknesses, materials and gate electrodes is calculated assuming tunneling only. We discuss the difference between gate and substrate injection and show quantitatively the impact of interfacial layer thickness, barrier height, k-value and the work function of the gate material on the tunneling current. In the second part the material properties are no longer considered to be independent and with the universal relation between k-value and barrier height introduced, we are able to identify what material suits best all requirements. The leakage current is calculated for different EOTs and we demonstrate that if all dielectrics follow this universal relation, for a fixed thickness there exists one material, which gives a minimum gate leakage current. It is concluded that even for sub 1nm EOT devices the k-value has not to exceed ∼25 and ZrO2 or HfO2 come closest to the ideal high-k if only leakage current issues are considered. [Copyright &y& Elsevier]

The reliability of ultra-thin silicon oxynitride gate dielectrics was investigated in terms of the Weibull slope of the tbd distributions, and the voltage acceleration factor. High field tBD statistics were extrapolated using a worst-case linear fit, to the low field region. The samples showed low voltage acceleration, which degrades reliability, but this is overcome by high Weibull slopes (β), which improve reliability. The high β values were investigated by monitoring the change in β as gate current increased during CVS. We saw the Weibull slope change from &ap;1 at low current to 2 at high current, indicating that breakdown results from 2-trap conduction. Charge pumping measurements showed that the trap generation rate at the SiON/Si interface, where most of the Nitrogen resides was very low. Thus it was concluded that there is a much higher trap generation rate in the bulk than at the interface and this is responsible for the values of β. [Copyright &y& Elsevier]

Abstract: The reliability of 0.69nm EOT GdHfO dielectric with metal gate is investigated. The threshold voltage shift at identical PBTI stress conditions is only 20% of the shift of a 0.78nm EOT HfO2 +La2O3 (or HfLaO) device. The resulting reliable gate over-drive at 10years of this GdHfO device is 0.85V. Analysis of the stress induced leakage current (SILC) shows that the improved PBTI in the GdHfO device is related to the reduced trap generation under low bias stress, which already exists in the HfLaO device. [Copyright &y& Elsevier]

The article discusses the means of improving the workfunction control of metal gate electrodes. The author cites that the key challenge for applying metal gates for metal-oxide-semiconductor field-effect transistor is the choosing of a metal with suitable workfunction. The author also defines a novel route to workfunction control through the alteration of the interface polarization layer by cautious deposition of dielectric stack and metal gate, then, by a temperature treatment.