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The phenomenological Landau–Ginzburg–Devonshire model provides a fundamental background for an understanding of the peculiar charge–voltage behavior of ferroelectric (FE) materials. However, the model cannot explain the polarization behavior of multidomain FE materials. The experimentally observed negative capacitance (NC) effect, which is interpreted as an emergence of the Landau barrier effect, involves particular conceptual difficulty. This work provides a new conceptual framework to explain the quasi‐static NC effect based on the energy formula for a stacked dielectric/ferroelectric (DE/FE) layer structure with the multidomain configuration with arbitrary shape. The presence of such domain configuration causes the energy–displacement curve of the inhomogenous Helmholtz energy term to have negative curvature. This is caused by the stray field between the neighboring domains. The model can be further extended to the DE/FE system with polycrystalline FE grains using the advanced phase‐field analysis. It is determined that the NC effect from the stray field is a universal phenomenon. These models provide quantitative explanations for the previously reported short‐pulse measurement results for various DE/FE material systems, which have lacked accurate interpretations. [ABSTRACT FROM AUTHOR]

The gate‐induced electrical instability of SnO thin‐film transistors (TFTs) with SiO2 and Al2O3/SiO2 gate dielectric layers is evaluated. The hysteresis voltage (Vhy) and threshold voltage (Vth) in the transfer characteristics of SnO TFTs depend on the sweep range and rate of gate voltage (VGS). The TFT with an Al2O3/SiO2 gate dielectric layer exhibit reduced Vhy and stable Vth compared with the device without an Al2O3 layer. The introduction of an Al2O3 layer between the SnO channel and the SiO2 layer suppresses the electron and hole trapping at the channel/dielectric interface and contains mobile oxygen vacancies that counteract the hole trapping effect. [ABSTRACT FROM AUTHOR]

HfO[SUB2]/Al[SUB2]O[SUB3] gate dielectric thin film stacks were deposited on Si wafers using the atomic layer deposition technique. A 3.3-nm-thick Al[SUB2]O[SUB3] interlayer was grown at 400 °C using Al(CH[SUB3])[SUB3] and O[SUB3], and 2.5-3.5-nm-thick HfO[SUB2] films were grown at either 300 or 400 °C using HfCl[SUB4] and H[SUB2]O. Thermal annealing of the dielectric film stack at temperatures ranging from 400 to 1000 °C under pure N[SUB2] atmosphere resulted in variation of the equivalent oxide thicknesses. The equivalent oxide thickness of the dielectric film stack showed a minimum after annealing at 650 °C irrespective of the HfO[SUB2] film growth temperature. High temperature (> 800 °C) annealing induced the formation of SiO[SUB2] and intermixing between the HfO[SUB2] and Al[SUB2]O[SUB3] layers, which resulted in an increase in the equivalent oxide thickness of the film stack. The structural changes in the stacked films as a function of the annealing temperature were compared with those of HfO[SUB2] and Al[SUB2]O[SUB3] single layers. The film stack showed minimal hysteresis (<15 mV) behavior in the capacitance-voltage curve and a shift in flat-band voltage of 0.6-0.9 V by negative fixed charges at the Al[SUB2]O[SUB3]/SiO[SUB2] interface after annealing at temperature >500 °C. The variation in fixed charge density as a function of the annealing temperature was also investigated. A minimum equivalent oxide thickness of 1.3 nm with leakage current density of 8 × 10[SUP-6]A/cm[SUP2] at -1 V was obtained with the poly-Si electrode even after annealing at 1000 °C for 10 s. This leakage current density is seven orders of magnitude smaller than that of SiO[SUB2] with similar equivalent oxide thickness. [ABSTRACT FROM AUTHOR]

The decrease in the measured dielectric constant of sputter-deposited (Ba, Sr)TiO[sub 3] thin films having Pt electrodes with decreasing dielectric film thickness was analyzed by a combination of theories regarding the finite charge-screening length of the metal electrode and the intrinsic-dead layer of the dielectric surface. It was found that the decreasing dielectric constant was mainly due to the metal electrode capacitance rather than the intrinsic-dead-layer capacitance. The almost film-thickness-independent dielectric constant of the (Ba, Sr)TiO[sub 3] thin films with conducting oxide electrodes, IrO[sub 2] and SrRuO[sub 3], when the dielectric film thickness >20 nm, was attributed to the very high capacitance values of the charge-screening layer of the oxide electrodes. The very high capacitance value appeared to originate from the strain-induced high dielectric constant of the oxide electrodes. [ABSTRACT FROM AUTHOR]

The thermal stress effects of the inter-level dielectric (ILD) layer on the ferroelectric performance of integrated Pt/SrBi[sub 2]Ta[sub 2]O[sub 9](SBT)/Pt capacitors were investigated. Two different thin film materials, pure SiO[sub 2] grown at 650 °C and B- and P-doped SiO[sub 2] grown at 400 °C by chemical vapor deposition techniques, were tested as an ILD layer. The ILD layer encapsulated the SBT capacitor array. During high temperature thermal cycling (up to 800 °C) after ILD deposition, which is used for both densifying the ILD and curing of the various damage imposed on the SBT capacitors, a large thermal stress occurred in the bottom Pt layer due to the thermal expansion mismatch between the various layers. In particular, the pure SiO[sub 2] ILD layer between the capacitors did not allow thermal expansion of the Pt layers, which led to a large accumulation of compressive stress in the layer. This resulted in hillock formation in the bottom Pt layer and eventual capacitor failure. However, the B- and P-doped SiO[sub 2] ILD layer contracted during thermal cycling by removing residual impurities, which allowed greater expansion of the Pt layer. Therefore, compressive stress accumulation did not occur and excellent ferroelectric properties were thus obtained from the integrated capacitor array. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Presents information on an article which reported variations of the leakage current density of capacitors after annealing. Experimental procedures; Results and discussion; Conclusion.

The effects of Zr composition on the crystallization behaviors and reliability characteristics of atomic-layer-deposited \Hf1-x\Zrx\Oy \ (\0 \leq x \leq \1) gate-dielectric films are examined. n-Channel metal–oxide–semiconductor field-effect transistor (nMOSFET) devices with \ZrO2 gate dielectrics showed a much smaller V \rm th shift under the positive bias stress compared with the same device with \HfO2 gate dielectrics. The impact of Zr composition on the crystallization temperature, crystalline phases, and surface morphology of \Hf1-x\Zrx\Oy films is studied. As the Zr composition in the \Hf1-x\Zrx\Oy films increased, the reduction of crystallization temperature and the transformation from a monoclinic to a tetragonal phase were observed. The grain size of the crystallized \ZrO2 film is much smaller than that of crystallized \HfO2. The flatband voltage (Vfb) shift under positive gate-bias stress in p-channel MOS capacitor (pMOSCAP) devices show a similar trend to the Vth shift in nMOSFET devices. In addition, the annealed \ZrO2 films show a large reduction in the Vfb shift under the positive bias stress compared with as-deposited \ZrO2 in pMOSCAP devices. The improved bias-temperature-instability characteristics of \ZrO2 compared with that of \HfO2 is related to the smaller grain size of crystallized \ZrO2. [ABSTRACT FROM AUTHOR]

The negative bias illumination temperature stress instability of amorphous Hf-In-Zn-O thin film transistors with different dimensions was evaluated. The threshold voltage (Vth) shift increased in devices with shorter channel lengths but showed almost no association with the channel width. This behavior was attributed to the diffusion and drift of the photogenerated holes at the channel/dielectric interface from regions near the drain to those near the source, which were due to the simultaneous presence of gate and drain biases. The Vth near the source, which shows the largest shift and hence has the highest local value, governs the overall Vth. [ABSTRACT FROM AUTHOR]

This letter examines the turn-around effect of a threshold voltage (Vth) shift of an n-type transistor with atomic-layer-deposited \HfOx\Ny gate dielectrics under a positive gate bias. Vth shifted to the positive voltage direction during the first second due to electron trapping at the preexisting trap sites in the gate dielectrics, which then shifted to the negative voltage direction. This turn-around effect was attributed to hole trapping originating from the generation of electron–hole pairs by the surface plasmon or impact ionization. [ABSTRACT FROM AUTHOR]

The frequency dispersion of the dielectric constant of yttrium (Y)-doped (Ba,Sr)TiO3 thin films (Y-BST) in the high-frequency domain (10 kHz–67 GHz) was investigated. In order to remove the substantial parasitic capacitances, inductances, and resistances from the measured impedance data, test samples, short-circuit standard, and open-circuit standard structures were fabricated and their frequency response was measured. Before removing parasitic components, the measured dielectric response showed a rolloff at approximately 4 GHz. However, after circuit calibration, the dielectric constant was almost constant up to 40 GHz where another rolloff was observed. However, this rolloff was due to the uncompensated small parasitic components. Therefore, the dielectric constant of the Y-BST films (170 with a film thickness of 30 nm) showed small frequency dispersion corresponding to the Curie–von Schweidler dispersion, of which the exponent is -0.0131, up to 40 GHz. Furthermore, the decrease of the capacitance was 17% in the frequency range from 10 kHz to 40 GHz. [ABSTRACT FROM AUTHOR]

The previously reported positive temperature coefficient of the resistivity (PTCR) observed in paraelectric BST thin films was again analyzed in terms of the non-Ohmic resistance as a result of an anode interface energy barrier induced by the high local charge density and interface energy states. The decrease in the low frequency dielectric constant, which is the dielectric constant relevant to the PTCR effect, with increasing temperature has a larger effect on the anode energy barrier than the temperature increase itself under a high bias voltage. In this case, the slope in the current-voltage curve at higher temperature decreases, which appears as the PTCR effect when the resistance is measured as a function of temperature under high voltages. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

The influences of low-dielectric interfacial layers on the dielectric properties of Pt/(Ba,Sr)TiO[sub 3]/Pt capacitors were investigated before and after postannealing. The interfacial layer is believed to be the intrinsic dead layer (low-dielectric layer) due to the termination of chemical bonds of the (Ba,Sr)TiO[sub 3] (BST) material at the interfaces. The dielectric constant of the capacitor decreases with decreasing BST film thickness owing to the low dielectric constant of the dead layer. The dead-layer capacitance varies with processes such as film deposition temperature, and postannealing. Higher deposition temperatures result in a larger dead-layer capacitance and a higher bulk dielectric constant. Although annealing under a N[sub 2] atmosphere is less effective in reducing the dead-layer effect than under an O[sub 2] atmosphere, it is more effective in increasing the bulk dielectric constant. Therefore, a N[sub 2], rather than an O[sub 2] atmosphere, results in a larger increase in the overall dielectric constant. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

The degradation behavior of integrated Pt/SrBi[sub 2]Ta[sub 2]O[sub 9]/Pt capacitors by hydrogen impregnation during the intermetal dielectric deposition and passivation is investigated. The hydrogen ions generated as a reaction byproduct from the SiH[sub 4]-based deposition processes of the dielectric films induce reduction in the remanent polarization (P[sub r]) as well as the imprint behavior of the small size capacitors (2x2 μm[sup 2]). The degree of degradation is quite dependent on the size of the individual capacitors. The smaller capacitors underwent more serious degradation implying that the hydrogen ions impregnate into the SBT layer mainly along the etched side area of the capacitors not through the top Pt electrode. Metallization adopting TiN/Al/TiN/Ti multilayer is very effective in suppressing the hydrogen impregnation. In particular, the Ti layer appears to block the hydrogen penetration. Therefore, the optimized metallization scheme, wider metal lines than the top electrode area by 1 μm, successfully protects the integrated capacitors from the hydrogen damage. 12 μC/cm2 of 2P[sub r] and 1.1 V of 2V[sub c] (coercive voltage) with an imprinting voltage of 0.16 V were obtained from the passivated 2x2 μm[sup 2] array capacitors by the optimized metallization. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Abstract: We investigate dielectric properties of rutile TiO2 using various exchange-correlation energy functionals such as local-density approximation (LDA), LDA + U method, and hybrid functionals. It is found that the computed dielectric constants significantly depend on the functional type, which originates from hardening or softening of phonon modes. While LDA provides the best result among the tested functionals, hybrid functionals and LDA + U methods significantly overestimate and underestimate dielectric constants, respectively. The underestimation by LDA + U is most alarming as it is not alleviated by adjusting lattice parameters, which implies that interatomic interactions are fundamentally affected by LDA + U. Furthermore, the LDA + U method also underestimates the dielectric constant of cubic SrTiO3. The present results suggest that special cares are needed in applying the LDA + U method to a system including TiO2 and SrTiO3. [Copyright &y& Elsevier]

Abstract: In this work, we have prepared metal–insulator–metal capacitors for dynamic random access memory capacitor application using atomic layer deposition of TiO2 high-κ dielectric and RuO2 bottom electrode. We compare TiO2 layers grown using TiCl4 precursor or Ti-tetra-isopropoxide precursor, and Al-doped TiO2 layers grown using Ti-tetra-isopropoxide precursor. The capacitors were analyzed in the terms of capacitance – voltage and current – voltage measurements and transmission electron microscopy imaging. [Copyright &y& Elsevier]