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In this work, we employ the substrate hot electron injection technique as a characterization tool to examine the defect creation mechanisms in high-k HfSiON gate stacks, taking advantage of the independent control over oxide field, electron fluence, and injected electron energy which the technique allows. We show that defect creation and oxide breakdown are dependent on the energy of the injected electrons and not on the oxide field. Furthermore, we show that the energy of the injected electrons governs whether the majority of the defects are created at the Si/SiO2 interface or in the bulk of the material. Results show that at operating conditions, the primary threat to device reliability from hot carrier damage is the introduction of a permanent 3D positive bias temperature instability component introduced by increased interface trap generation, even for carriers with energy slightly above that of field accelerated electrons. We also discuss the feasibility of using substrate hot electron injection as a means to accelerate time dependent dielectric breakdown measurements, thereby allowing degradation at lower oxide fields to be probed. [ABSTRACT FROM AUTHOR]

The charge trapping is studied in metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with SrBi2Ta2O9 (SBT)/Al2O3/SiO2 gate stack by high-frequency and pulsed capacitance-voltage (CV) measurements. The ferroelectric polarization is observed by high-frequency CV. Under fast gate voltage sweep in pulsed CV, the delay of electron trapping detrapping in the buffer layer induces an opposite CV hysteresis direction than that of the ferroelectric polarization. For memory programming, the hole trapping in the gate stack limits the electric field in SBT. Furthermore, the electron trapping during stress induces serious threshold voltage instability as well as erratic memory read out. All these charge trapping problems are important for the practical application and reliability of the memory with MFIS structure. [ABSTRACT FROM AUTHOR]

Silicon bandgap limits the reduction of operation voltage when downscaling device sizes. This increases the electrical field within-a-device and hot carrier aging (HCA) is becoming an important reliability issue again for some CMOS technologies. For nanodevices, there are a number of challenges for characterizing their HCA: the random charge–discharge of traps in gate dielectric causes “within-a-device-fluctuation (WDF),” making the parameter shift uncertain after a given HCA. This can introduce errors when extracting HCA time exponents and it will be shown that the lower envelope of the WDF must be used. Nanodevices also have substantial device-to-device variation (DDV) and multiple tests are needed for evaluating their standard deviation ( $\sigma )$ and mean value ( $\mu $ ). Repeating the time-consuming HCA tests is costly and a voltage-step-stress method is applied to reduce the number of tests by 80%. For a given number of devices under tests (DUTs), there is a little information on the accuracy of the extracted $\sigma $ and $\mu $ . We will develop a method to provide this information, based on the defect-centric model. For 40 DUTs with an average of ten traps per device, the extracted $\mu $ and $\sigma $ has an accuracy of ±14% and ±24%, respectively, with a 95% confidence. [ABSTRACT FROM PUBLISHER]

We propose a novel spectroscopic technique that allows determining the defect density distributions within metal-electrode-sandwiched dielectric based on $J$ – $V$ and $C$ – $V$ characteristics. The technique relies on determining “sensitivity regions” corresponding to the energy-spatial coordinates of defects affecting $J$ – $V$ and $C$ – $V$ curves. This technique is then demonstrated on RuOx/SrTiOx/RuOx metal–insulator–metal structures for DRAM capacitor applications. [ABSTRACT FROM PUBLISHER]

The access transistor of SRAM can suffer both positive bias temperature instability (PBTI) and hot carrier aging (HCA) during operation. The understanding of electron traps (ETs) is still incomplete and there is little information on their similarity and differences under these two stress modes. The key objective of this paper is to investigate ETs in terms of energy distribution, charging and discharging properties, and generation. We found that both PBTI and HCA can charge ETs which center at 1.4 eV below conduction band ( Ec ) of high-k dielectric, agreeing with theoretical calculation. For the first time, clear evidences are presented that HCA generates new ETs, which do not exist when stressed by PBTI. When charged, the generated ETs’ peak is 0.2 eV deeper than that of preexisting ETs. In contrast with the power law kinetics for charging the preexisting ETs, filling the generated ETs saturates in seconds, even under an operation bias of 0.9 V. ET generation shortens device lifetime and must be included in modeling HCA. A cyclic and antineutralization ETs model is proposed to explain PBTI and HCA degradation, which consists of preexisting cyclic ETs, generated cyclic ETs, and antineutralization ETs. [ABSTRACT FROM AUTHOR]

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si-pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO2/Al2O3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the time exponent varies with stress biases/field when measured by either the conventional slow dc or pulse I-V technique, making the conventional Vg -accelerated method for predicting the lifetime of Si-pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO2/Al2O3 can be fully annealed at 150 ^\circC ; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., Ev , when neutral, lift well above Ev after charging, and return below Ev following neutralization. [ABSTRACT FROM PUBLISHER]

Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a \SiO2/ \HfO2 dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups. [ABSTRACT FROM PUBLISHER]

The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H^+ species released from the Si/SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H^+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs. [ABSTRACT FROM PUBLISHER]

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of \Si/SiO2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI. [ABSTRACT FROM AUTHOR]

A methodology to incorporate the MOSFET gate dielectric breakdown (BD) failure mechanism in the design of complex systems is presented. The model accounts for the statistical nature of the BD phenomenon, is easily extensible to different device geometries and operation conditions (following the established scaling rules for the mechanism), considers the stress history, and can be easily implemented in circuit simulation tools. Device level characterization of the BD mechanism is presented, which is the base for model parameter extraction. The model has been introduced in a circuit simulator to show its suitability for evaluation of the BD effect in circuits and their reliability, taking ring oscillators as example. [ABSTRACT FROM PUBLISHER]

Interface states play an important role in the performance of MOSFETs, and previous works only addressed the states within band gap. The implicit assumption is that the states beyond band gap (SBBs) are negligible, but there is no experimental evidence supporting it. Because of a lack of techniques for characterizing SBBs, there is hardly any information available. The central objective of this paper is to develop a technique for evaluating SBBs and to show the impact of SBBs on mobility evaluation. For the first time, the pulse capacitance–voltage has been used to extract SBBs quantitatively. It is found that SBBs can reach the order of \10^13 \ \cm^-2\cdot\eV^-1 beyond both conduction- and valence-band edges on a fresh MOSFET. The conventional split C– V technique ignores the SBBs, and this can lead to an underestimation of carrier mobility over 30%. Using the newly developed technique as a tool, the impact of nitridation of Hf-based dielectric stacks on carrier mobility is assessed. As nitrogen density increases, the apparent reduction of carrier mobility observed by early works originates from the higher SBBs. Once SBBs are taken into account, nitridation does not degrade carrier mobility. The SBBs are sensitive to process conditions, and this paper opens the way for their minimization. [ABSTRACT FROM AUTHOR]

Characterizing interface states is a key task, and it typically takes seconds when conventional techniques, such as charge pumping (CP), are used. The stress-induced degradation can recover substantially during this time, and there is a need to improve the measurement speed. The central task of this work is to reduce the measurement time for interface states from seconds to microseconds to minimize the recovery. A fast single pulse CP (SPCP) technique is developed. By exploring the differences in the transient currents corresponding to the two edges of the gate pulse, the net charges pumped into devices can be obtained, and their saturation level is used to evaluate interface states. Unlike the conventional CP (CCP) method, the contribution of currents during the plateaus of gate pulse is excluded for SPCP, making it less vulnerable to the interferences of gate leakage and defects within dielectrics. For the first time, the SPCP allows the recovery of interface states being monitored with a time resolution in microseconds. The results show that the recovery of stress-induced interface states is substantial within 100 \mu\s, which would be missed if the CCP were used. [ABSTRACT FROM PUBLISHER]

A fast response technique is developed to investigate the short-term postprogram and post-erase discharge in Flash memory devices. The procedure is based on fast VTH -evaluation methods developed for bias temperature instability and provides the transient characteristics after 20 ms under the program or erase conditions. The following different structures are investigated: 1) \SiO2/high-k stacks; 2) charge trap memories; 3) and floating gate memories. Dielectrics targeted for Flash memory applications are used as charge trap layers and interpoly dielectrics. In this paper, we show results on \Al2\O3, DyScO, GdScO, and hexagonal and perovskite LuAlO. The postprogram and post-erase curves hold useful information about the dielectric properties and are used as a fast screening technique for alternative materials. [ABSTRACT FROM PUBLISHER]

Strontium titanate (STO) is a dielectric with a cubic perovskite type structure and of increasing interest for microelectronics, especially in the metal-insulator-metal (MIM) capacitors due to its high dielectric constant. The dielectric constant of the STO films and consequently the performance of the MIM capacitors appear to be strongly influenced by the process conditions. In this work the authors report on the influence of various thermal treatments upon the crystallinity and morphology of strontium titanate crystals. The influence of spike, laser, or rapid thermal anneals on the morphology with respect to grain size and topography of the crystalline stoichiometric STO films is studied. Also, the use of a stack containing a Sr-rich STO (62% Sr) bottom seed layer and a stoichiometric STO top layer in combination with a thermal treatment was found to affect the microstructure of the STO film. A comparison of the electrical properties for various thermal treatments has been made. [ABSTRACT FROM AUTHOR]

Predicting negative bias temperature instability (NBTI) lifetime can be dangerous since it is difficult to assess its safety margin. The common technique uses gate bias Vg acceleration to reduce the test time, and the data were typically obtained from quasi-dc measurements. Recently, it has been shown that substantial recovery occurs during the quasi-dc measurement, and the suppression of recovery requires using ultrafast pulse measurement, where time was reduced to the order of microseconds. In a real circuit, different transistors have different levels of recovery, and the worst case scenario is when recovery is suppressed. At present, there is little information on how this worst case NBTI lifetime can be predicted and whether the traditional Vg acceleration technique can still be used. This work will show that the prediction based on the Vg acceleration results in a substantial error, and its cause will be analyzed. To predict the worst case lifetime, a model for NBTI kinetics under operation gate bias is developed. This kinetics includes contributions from both as-grown and generated defects, and it no longer follows a simple power law. Based on the new kinetics, a single-test prediction method is proposed, and its safety margin is estimated to be 50%. [ABSTRACT FROM AUTHOR]

In this paper, we study time-dependent dielectric breakdown in thin gate oxides and propose a new methodology applicable to a wide range of gate stacks for extracting breakdown (SBD) and post-SBD wear-out (WO) parameters measuring the time to hard breakdown (tHBD) only. By introducing this methodology, we can get around the problems related to the detection of the first SBD and the corresponding WO time. We show that the shape of the HBD distribution can change with voltage and area, depending on the ratio of WO and SBD times. We also explain why, in literature, contradictory results related to the voltage acceleration factors of SBD and WO are reported. Finally, we construct a complete reliability prediction model includes SBD and WO. [ABSTRACT FROM AUTHOR]

A theory of the current-ratio (CR) technique in uniform semiconductors, which is widely used to locate gate oxide breakdown (BD) spots in one dimension (i.e., distance from source or drain), is proposed and verified. The theory shows that the CR method is a special case of generalized van der Pauw technique and, as such, can easily be generalized to locate oxide BD spots in two dimensions. We develop the theoretical framework of this new class of BD-spot characterization techniques and then validate the theory by experiments. We conclude by discussing the implications of locating BD spots in two dimensions for reliability projections of ultrathin gate oxides. [ABSTRACT FROM AUTHOR]

Based on the so-called defect-centric statistics, we propose the average impact of a single charged trap on FET threshold voltage as a physically based measure of the random component of time-dependent variability. We show that it can be extracted using matched pairs, analogously to time-zero variability. To that end, the defect-centric statistics of matched pairs are discussed and the correlation between time-zero and time-dependent variances is formalized. [ABSTRACT FROM AUTHOR]

The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO2 and HfO2 dielectrics with metal gate is investigated. The threshold voltage shift (\DeltaVTH) at identical NBTI over-drive stress conditions is observed to be lower in ZrO2 than in HfO2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation (\DeltaNit) in the sub-1-nanometer EOT devices, with ZrO2 devices showing about one order of magnitude lower \DeltaNit than HfO2 device. However, the \DeltaNit contribution to the total \DeltaVTH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id–Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO2, which decisively reduces NBTI in ZrO2 gate dielectric. [ABSTRACT FROM PUBLISHER]

In this letter, submelt laser anneal used to achieve ultrashallow junctions (USJs) in capped high-k devices with TaN/ TiN metal gate electrode is investigated. The submelt laser anneal results in USJ and sharp junction on both n- and pMOSFET devices. However, this process induces interface and bulk defects and reduces negative-bias temperature instability (NBTI) reliability additionally. It is shown that if the laser anneal is followed by a rapid thermal anneal, the laser-related damage decreases, and the NBTI robustness improves without altering the obtained junction sharpness. [ABSTRACT FROM AUTHOR]

The reliability of ultra-thin silicon oxynitride gate dielectrics was investigated in terms of the Weibull slope of the tbd distributions, and the voltage acceleration factor. High field tBD statistics were extrapolated using a worst-case linear fit, to the low field region. The samples showed low voltage acceleration, which degrades reliability, but this is overcome by high Weibull slopes (β), which improve reliability. The high β values were investigated by monitoring the change in β as gate current increased during CVS. We saw the Weibull slope change from ≈1 at low current to 2 at high current, indicating that breakdown results from 2-trap conduction. Charge pumping measurements showed that the trap generation rate at the SiON/Si interface, where most of the Nitrogen resides was very low. Thus it was concluded that there is a much higher trap generation rate in the bulk than at the interface and this is responsible for the values of β. [Copyright &y& Elsevier]

Dielectric defects play a crucial role in the reliability of MOSFETs. In this study, we aim to gain a deeper understanding of dielectrics' degradation by correlating the effective interface (N 2 D) and bulk (N B T) trap densities extracted by different characterization techniques (I-V, charge pumping, and 1/f noise) under different electrical stress conditions. Additionally, we establish an empirical relation between the increase of N B T (estimated via 1/f noise measurements) and N 2 D , e f f (estimated through the monitoring of threshold voltage shift) after stress. This relation is useful to calculate the expected increase in 1/f noise from the V T degradation models typically made available by the foundries to circuit designers. • Comparison of electrical techniques to extract trap densities under diverse stress conditions. • 1/f noise increases with stress only in the carrier number fluctuation regime (i.e., at low gate voltage overdrives). • We derive an empirical relationship between the stress-induced increase of 1/f noise and threshold voltage shift. [ABSTRACT FROM AUTHOR]

Abstract: The post-breakdown conduction properties of ultrathin SiON layers were investigated, to determine the impact of various parameters on the growth of a breakdown path after its formation. Post-breakdown conduction is seen to be dependent on stress voltage used to break the oxide, the stress temperature, and the time-to-breakdown. With this knowledge, the performance of transistors of various channel lengths and widths was studied both before and after breakdown occurred to determine whether the devices still function as a digital switches after breakdown. That is, the drain to source current (I ds) in the on–state (V g ≫ V th) is much larger than I ds in the off–state (V g < V th), allowing the device to continue to function as a switch, after breakdown occurs. [Copyright &y& Elsevier]

Abstract: Hafnium silicate had been suggested as a possible ‘mid-k’ alternative to SiON as a gate dielectric for the 45 nm technology node. This work focuses on the shift in threshold voltage, the degradation in transconductance, and the sub-threshold swing during oxide stress. Analysis of these parameters reveals much about the trap generation mechanisms in the layers, as well as differences from SiON. The effect of the aspect ratio dimensions on post-breakdown device functionality is also discussed. [Copyright &y& Elsevier]

Abstract: The reliability of 0.69nm EOT GdHfO dielectric with metal gate is investigated. The threshold voltage shift at identical PBTI stress conditions is only 20% of the shift of a 0.78nm EOT HfO2 +La2O3 (or HfLaO) device. The resulting reliable gate over-drive at 10years of this GdHfO device is 0.85V. Analysis of the stress induced leakage current (SILC) shows that the improved PBTI in the GdHfO device is related to the reduced trap generation under low bias stress, which already exists in the HfLaO device. [Copyright &y& Elsevier]