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ZrTiOx-based metal–insulator–metal (MIM) devices with both-sided, one-sided, and without interfacial layer (IL) were fabricated by employing Ni or TaN as the electrodes to investigate the impact of presence and position of IL on the resistive switching behaviors. The IL plays a critical role in determining the magnitude of SET and RESET voltage since the oxygen vacancies and trapped electrons in the IL modulate the effective electric field in the ZrTiOx. With Ni and TaN as the top and bottom electrode, respectively, devices demonstrate self-compliance and bipolar switching behavior without requiring a forming step. The devices also exhibit great potential for next-generation nonvolatile memory applications because of the promising characteristics such as low dc SET/RESET voltage of 0.9/−0.6 V, tight distribution of device parameters, high switching speed of 200 ns with ±1.3 V, a large memory window of 6000 times, robust endurance up to 106 cycles, and good retention. [ABSTRACT FROM PUBLISHER]

An amorphous Yb2O3 passivation layer integrated with a crystalline ZrTiO4 film was explored as the advanced gate stack for Ge MOS devices. The ZrTiO 4/Yb2O 3 gate stack demonstrates Dit of 2.4 × 10^11 cm ^-2\cdot\, eV^-1 and EOT down to 0.76 nm which are, respectively, due to the formation of an interfacial YbGeO x layer that well passivates the dangling bonds at Ge surface and the adoption of a crystalline ZrTiO4 film with a κ value of 45.6. The gate stack also shows low leakage current, tight distribution of device parameters, and desirable reliability performance, paving an alternative avenue to develop high-performance Ge MOS devices. [ABSTRACT FROM PUBLISHER]

Highlights: [•] Investigate the impact of dielectric crystallinity on the performance of RRAM. [•] Provides more insights into the different conduction mechanisms for RRAM operation. [•] Amorphous ZrTiO x outperforms crystalline ZrTiO x for RRAM applications. [Copyright &y& Elsevier]

An amorphous (ZrO_2) _x(La _2O_3) 1-x alloy formed by depositing a ZrO _2/La_2O _3/ZrO_2 laminate and a subsequent annealing was employed as the gate dielectric for metal-oxide-semiconductor (MOS) devices. The (ZrO_2) _x(La_2O_3)1-x alloy is found to have a high permittivity κ of 26.2 with negligible amount of bulk traps, both of which are very desirable for advanced gate dielectrics. By integrating the (ZrO_2)_x(La _2O_3) 1-x alloy with an SiON interfacial layer as the gate stack, it displays good frequency dispersion in capacitance–voltage (C –V) characteristics and low interfacial trap density of 1.52 × 10^11 cm^-2 eV^-1. In addition, the current conduction mechanism of the gate stack is observed to be Fowler–Nordheim tunneling and the leakage current of 3.6 × 10^-6 A/cm^2 at the gate voltage of −1 V for equivalent oxide thickness of 1.1 nm can be achieved, which is superior to other high-κ dielectrics. Furthermore, satisfactory reliability is verified by bias temperature instability measurement. Most importantly, this gate stack not only exhibits a promising perspective for advanced CMOS technology but introduces a more reliable process to form an alloy-based high-κ gate dielectric. [ABSTRACT FROM PUBLISHER]

Ge MOS devices passivated by SmGeOx with equivalent oxide thickness of 0.61 nm were employed as the platform to evaluate the eligibility of SmGeOx as Ge surface passivation layer. The SmGeOx layer was formed by deposition of Sm2O3 on Ge substrate with a subsequent O2 annealing and the formation of SmGeOx was confirmed by X-ray photoelectron spectroscopy. The tiny frequency dispersion in capacitance measurement and a low interface trap density of 5.1\times 10^11~cm^-2eV^-1 near midgap attest to desirable passivation effect and it can be ascribed to Sm-Ge-O bonding, which is favorable in mitigating dangling bonds at Ge surface. In addition, the small hysteresis in capacitance also suggests good quality of bulk dielectric. Due to the small amount of bulk traps and large conduction band offset with respect to Ge, it enjoys low leakage current of 0.36 A/cm^2 at gate bias of Vfb (flatband voltage)-1 V. Through the test of bias temperature instability, the passivation layer demonstrates reasonable reliability performance in terms of 65-mV flatband voltage shift at 85^\circC after stressing with -16~MV/cm for 1000 s. With these characteristics, SmGeOx is promising as a passivation layer for aggressively scaled Ge MOS devices. [ABSTRACT FROM AUTHOR]

TaN/ZrTiOx/Pt metal-insulator-metal structure was employed as the platform to evaluate the eligibility for antifuse one-time programmable (OTP) memory applications, and the impact of O2 plasma on device performance was also discussed. Owing to the oxygen radicals that enhance the dielectric integrity, the voltage for state switching increases with O2 plasma treatment. Memory cells without plasma treatment demonstrate promising characteristics for OTP memory applications in terms of a low dc switching voltage of 2 V, high programming speed of 60 ns, high read endurance up to 10^6 reading cycles, and desirable retention time and low switching power density of 6.4 mW/cm^2. The memory cell technology not only exhibits the prominent performance which is advantageous over other dielectrics reported in the literature, but it also possesses the capability to from stackable 3-D architecture. [ABSTRACT FROM PUBLISHER]

Perovskite-based BaZry\rm Ti1-y\rm O3 (BZTO) (y=0.6) with partial crystallization has been found to possess a rather high-\kappa value of 48.6 and positive quadratic voltage coefficient of capacitance (VCC). Through stacking BZTO and ZrTiOx as laminate dielectric, metal–insulator–metal capacitors using VCC canceling effect advance frontiers by exhibiting a record-low VCC of 14 ppm/V^2 at the capacitance of 13.4 fF/\mum^2, low dielectric loss tangent <0.01, and low leakage current of 7.5\times 10^-9~A/cm^2 at -1~V. With constant voltage stress at 2.5 V for 1000 s, degradation in leakage current <30\% is observed. In addition, excellent reliability of 0.89% capacitance change against stress up to a projected of 10 years is also achieved. The aforementioned characteristics not only compare favorably to other high-\kappa-based dielectrics, most importantly, but also these results meet ITRS requirements set by 2024. [ABSTRACT FROM AUTHOR]

Because of a higher permittivity than \Al2\O3, a large conduction band offset and high thermal stability, a thin amorphous \Yb2\O3 layer was integrated with a \ZrTiO4 film as the gate stack for advanced Si MOS devices. With 800 ^\circ\C annealing, the \ZrTiO4 film can be crystallized in orthorhombic phase with permittivity of 45.9 and a gate stack with equivalent oxide thickness of 0.86 nm can be achieved. This crystalline \ZrTiO4/\Yb2\O3 gate stack demonstrates negligible frequency dispersion in capacitance, low interface trap density of \1.86 \times \10^11\ \cm^-2\eV^-1 , leakage current of \6.7 \times \10^-6\ \A/cm^2 at gate bias of flatband voltage (VFB)-1\ \V, and high extrapolated 10-year lifetime operating voltage of -2.9 V. These promising electrical characteristics suggest that the crystalline \ZrTiO4/\Yb2\O3 gate stack holds great potential to be applied to aggressively scaled CMOS technology. [ABSTRACT FROM AUTHOR]

Metal-insulator-metal (MIM) capacitors with single \TiO2 and a \TiO2/\Y2\O3 stack as an insulator are explored in this letter. It is found that, at the process temperature higher than 400 ^\circ\C, \TiO2 MIM capacitors demonstrate a high capacitance density at the price of an unacceptably high leakage current and voltage coefficient of capacitance (VCC). On the other hand, with the process temperature of 500 ^\circ\C, \TiO2/\Y2\O3 MIM capacitors display desirable characteristics in terms of a large capacitance density of 32.2 \fF/\mu\m^2, a low VCC of 3490 \ppm/ \V^2, small frequency dispersion, and a low leakage current of \4.5\! \times\! \10^-9\ \A/\cm^2 at -1 V. The \Y2 \O3 film not only provides a high dielectric–electrode band offset but also possesses high thermal stability against crystallization; both are important to suppress leakage current. In addition, the \Y2\O3 film prevents a \TiO2 film from crystallization at 500 ^\circ\C due to the increased entropy caused by incorporated Y atoms, and the amorphous \TiO2 film offers a high \kappa value to achieve a large capacitance density without sacrificing leakage current and VCC. [ABSTRACT FROM AUTHOR]

\SnGeOx films formed by thermal oxidation of Sn/Ge and \SnGex/\Ge structures were confirmed by X-ray photoelectron spectroscopy and explored to investigate the capability of passivation for Ge MOS devices. It is found that Sn incorporation into germanium oxide is effective in suppressing the formation of volatile GeO. For \SnGeOx films formed by oxidation of \SnGex/\Ge structures, due to fewer dislocations between \SnGex and Ge, it enjoys an interface trap density of \2.1 \times \10^11\ \cm^-2 \cdot \eV^-1, which is lower than those oxidized from Sn/Ge structures. Furthermore, the films also demonstrate desirable electrical characteristics in terms of tiny frequency dispersion and small hysteresis in capacitance measurement, a low leakage current of \9.3 \times \10^-10\ \A/cm^2 at a gate voltage of -1 V with an effective oxide thickness of 3.6 nm, and a good bias temperature instability of 15-mV flatband voltage shift at 85 ^\circ\C after 12.5 MV/cm stress for 1000 s. [ABSTRACT FROM AUTHOR]

A Ge-stabilized tetragonal ZrO2 dielectric with a permittivity (κ) value of 36.5 has been obtained by annealing a ZrO2/Ge/ZrO2 laminate at 500 °C and it is a more reliable approach toward stabilizing a tetragonal ZrO2 film. However, metal-insulator-metal (MIM) capacitors with the sole tetragonal ZrO2 film as an insulator achieve a high capacitance density of 27.8 fF/μm2 at the price of a degraded quadratic voltage coefficient of capacitance (VCC) of 81 129 ppm/V2 and unacceptably high leakage current. By capping an amorphous La-doped ZrO2 layer with a κ value of 26.3 to block grain boundaries-induced leakage paths of the crystalline ZrO2 dielectric, high-performance MIM capacitors in terms of a capacitance density of 19.8 fF/μm2, a VCC of 3135 ppm/V2, leakage current of 6.5×10-8 A/cm2 at -1 V, as well as a satisfactory capacitance change of 1.21% after ten-year operation can be realized. [ABSTRACT FROM AUTHOR]