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In this work, we demonstrate the use of a machine learning (ML)-based statistical approach to model and analyze the impact of the fabrication processes on the threshold voltage in recessed gate AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors. First, we employ a ML-based Tikhonov regularization approach using the input of 19 different processing splits to generate a multivariable analytical equation that considers four critical processing parameters, such as the remaining AlGaN depth, ex-situ wet clean, in-situ plasma, and gate dielectric. Furthermore, the artificial neural network-based approach, which cannot be used to further analyze the impact of the process, is implemented for the comparison. Second, the results from this analytical equation show a nice agreement with the measured threshold voltage, indicating a successful correlation between the processing parameters and the threshold voltage. Finally, the impact of each process on the threshold voltage can be analyzed through the coefficient value related to each process, which can be a useful guidance for the device optimization toward the targeted performance. [ABSTRACT FROM AUTHOR]

In this letter, we investigate annealing effects in ferroelectric HfZrOx dielectric in metal–insulator–metal devices and metal–oxide–semiconductor capacitors by comparing two annealing methods: rapid thermal annealing (RTA) and microwave annealing (MWA). The tradeoff characteristics between the annealing conditions, polarization–electric field characteristics, gate leakage current, and interface state density (${D} _{\textsf {it}}$) are discussed. We show that: 1) a positive correlation between the remanent polarization (Pr), the gate leakage current, and ${D}_{\textsf {it}}$ as the annealing temperature (RTA) and the annealing power (MWA) increase and 2) the MWA is promising for ferroelectric transistors technology, since its low thermal budget can minimize ${D}_{\textsf {it}}$ and avoid increase in the gate leakage current. [ABSTRACT FROM AUTHOR]

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al2O3 gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxation. Hence, a defect band model with different distributions of defect levels inside the gate dielectric is proposed, which can excellently reproduce the experimental data and provide insightful information about the origin of PBTI in GaN MISFETs. The results indicate that the serious PBTI in the device with PEALD SiN is mainly due to a wide distribution of defect levels ( \sigma \sim 0.67 eV), centered below the conduction band of GaN ( E_{C} -0.05 eV), and can be easily accessed by the channel carriers already at a low-gate voltage. On the other hand, ALD Al2O3 gate dielectric shows a narrower distribution of defects ( \sigma \sim 0.42$ eV), which are far from the conduction band of GaN ( E_{C} +1.15 eV). This observations explain the improved PBTI reliability observed in devices with ALD Al2O3. [ABSTRACT FROM AUTHOR]

We focus on slow de-trapping phenomena in AlGaN/GaN MIS-HEMTs with a bilayer dielectric ( in-situ Si 3 N 4 /Al 2 O 3 ) with two different thicknesses of in-situ Si 3 N 4 (10 nm and 5 nm). By using a “filling pulse” at a positive gate voltage, a trap with activation energy of 0.69–0.7 eV was identified to be responsible for the V TH shift. Based on literature, filling conditions, and the simulated band diagrams, this trap is most probably located at the interface between the dielectrics and AlGaN barrier. A physical model is proposed to explain the V TH shift due to the trapping/de-trapping phenomena based on the occupation dynamics of donor traps at the interface between the in-situ Si 3 N 4 /Al 2 O 3 and the AlGaN barrier. [ABSTRACT FROM AUTHOR]

In this work, the time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs with two different structures, i.e., planar and trench gate structures. We have discovered different gate leakage current behaviors between the SiC MOSFETs with planar gate (Sample A) and trench gate (Sample B) during the forward gate bias stress. Notably, the slight increase of the gate current during the stress and the negative activation energy (E a = −0.07 eV) observed in Sample A suggest that the hole generation caused by the impact ionization can be occurred during the forward gate TDDB tests. Furthermore, the SiC MOSFETs with trench gate structure (Sample B) exhibit the operation voltage of 55.7 V (exponential law) and 57.3 V (power law) for the 0.001 % failure of 30 years under 175 °C, indicating that SiC trench gate MOSFETs with enough thick gate dielectric (87.1 nm (bottom) and 77.9 nm (sidewall)) can have the promising forward gate TDDB stability. • The time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs • Different gate leakage current behaviors between the SiC MOSFETs with planar gate and trench gate • The negative activation energy observed in SiC planar MOSFETs suggests that the hole generation caused by the impact ionization • SiC trench gate MOSFETs with enough thick gate dielectric can have the promising forward gate TDDB stability. [ABSTRACT FROM AUTHOR]

In this work, the relaxation analysis is performed to understand the V TH instability in FeFETs with two different dopants, i.e., Si and Gd. The FeFETs with different dopants show the different delay-after-write characteristics, i.e., Gd:HfO 2 FeFETs show a better delay-after-write stability compared to the case of Si:HfO 2 FeFETs. With the relaxation analysis, Si:HfO 2 FeFETs exhibit an obvious V TH recovery during the relaxation phases. Furthermore, the power law fitting is used to analyze the V TH shift under the positive program bias, indicating that a wide and easily accessible defects can exist in the IL and/or Si:HfO 2 since the smaller overdrive voltage dependence exponent (γ) is obtained in Si:HfO 2. Last, the smaller V TH shift/recovery in Gd:HfO 2 FeFETs can be attributed to a relatively tighter defect distribution, indicating that the dopants in the ferroelectric layer and the defects in IL and/or ferroelectric dielectric have to be carefully optimized to achieve the better V TH stability. • Si:HfO 2 FeFETs exhibit an obvious V TH recovery during the relaxation phases. • The power law fitting is used to analyze the V TH shift, indicating that a wide and easily accessible defects can exist in the IL and/or Si:HfO 2. • The smaller V TH shift/recovery in Gd:HfO 2 FeFETs indicates that the dopants and the defects have to be carefully optimized to achieve the better V TH stability. [ABSTRACT FROM AUTHOR]