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Defect generation in HfO[sub 2]/SiO[sub 2] gate dielectric stacks under constant voltage stress is investigated. It is found that the stress induced electrical degradation in HfO[sub 2]/SiO[sub 2] stacks is different than in the SiO[sub 2] layer. The variation of the gate leakage current with different polarities shows different degradation characteristics after stress. Positive charge generation is also observed under both negative and positive gate voltage polarities. These degradation phenomena are explained by the composite effect of three components: neutral trap generation, electron trapping, and positive charge generation in the gate stacks. [ABSTRACT FROM AUTHOR]

The problem of k-value degradation (plasma damage) is a key issue for the integration, and it is becoming more challenging as the dielectric constant of low-k materials scales down. One way to circumvent this issue is temporarily conversion of low-k material from a porous to a dense state by filling the pores with a sacrificial polymer after the deposition and curing of the low-k material. A detailed process scheme for the pore stuffing and postetch polymer removal of PMMA is described in this work. The filling temperature was optimized according to the molecular weight of the PMMA. To remove the polymer after plasma-etching in a purely thermal environment, a temperature of at least 430 °C had to be applied. Annealing assisted by variable frequency microwaves could remove the polymer already at 380 °C and with a He-H2 afterglow plasma the polymer could be removed at 280 °C. Laser annealing allowed the removal at a stage temperature of 200 °C with an only surface-limited heating of about 500 °C and higher to prevent the FEOL structures from damage. This work presents the results of the detailed study of stuffing and unstuffing processes, discusses mechanisms, and provides background for a robust stuffing and polymer removal process for the plasma damage reduction in porous low-k dielectrics. [ABSTRACT FROM AUTHOR]

Interface states play an important role in the performance of MOSFETs, and previous works only addressed the states within band gap. The implicit assumption is that the states beyond band gap (SBBs) are negligible, but there is no experimental evidence supporting it. Because of a lack of techniques for characterizing SBBs, there is hardly any information available. The central objective of this paper is to develop a technique for evaluating SBBs and to show the impact of SBBs on mobility evaluation. For the first time, the pulse capacitance–voltage has been used to extract SBBs quantitatively. It is found that SBBs can reach the order of \10^13 \ \cm^-2\cdot\eV^-1 beyond both conduction- and valence-band edges on a fresh MOSFET. The conventional split C– V technique ignores the SBBs, and this can lead to an underestimation of carrier mobility over 30%. Using the newly developed technique as a tool, the impact of nitridation of Hf-based dielectric stacks on carrier mobility is assessed. As nitrogen density increases, the apparent reduction of carrier mobility observed by early works originates from the higher SBBs. Once SBBs are taken into account, nitridation does not degrade carrier mobility. The SBBs are sensitive to process conditions, and this paper opens the way for their minimization. [ABSTRACT FROM AUTHOR]

Characterizing interface states is a key task, and it typically takes seconds when conventional techniques, such as charge pumping (CP), are used. The stress-induced degradation can recover substantially during this time, and there is a need to improve the measurement speed. The central task of this work is to reduce the measurement time for interface states from seconds to microseconds to minimize the recovery. A fast single pulse CP (SPCP) technique is developed. By exploring the differences in the transient currents corresponding to the two edges of the gate pulse, the net charges pumped into devices can be obtained, and their saturation level is used to evaluate interface states. Unlike the conventional CP (CCP) method, the contribution of currents during the plateaus of gate pulse is excluded for SPCP, making it less vulnerable to the interferences of gate leakage and defects within dielectrics. For the first time, the SPCP allows the recovery of interface states being monitored with a time resolution in microseconds. The results show that the recovery of stress-induced interface states is substantial within 100 \mu\s, which would be missed if the CCP were used. [ABSTRACT FROM PUBLISHER]

The role of moisture (H[sub2]O) in atomic-layer-deposited (ALD) HfO[sub2∙] and HfSiO[sub2∙] dielectrics on equivalent oxide thickness (EOT) scaling is investigated in gate-first devices with physical-vapor-deposited TaN gates. By reducing the amount of H[sub2]O present in the gate stack, the EOT increase during high-temperature (1030°C) spike annealing is reduced from 0.5 to0.25 nm. This was achieved by a premetallization degas at 350-550°C for 3 mm. The origin of this improvement lies in the elimination of H[sub2]O-related reoxidation of the interfacial SiO[sub2]. By means of temperature-programmed desorption measurements, it is found that the majority of the H[sub2]O is desorbed between 200 and 600°C with activation energies between ∼0.3 and -0.5 eV. Furthermore, the H[sub2]O concentration is dependent on the Hf concentration and nitridation. Non-nitrided HfSiO[sub2∙] with [Hf] = 40% adsorbs twice as much H[sub2]O as HfO[sub2∙]. Correspondingly, a significantly larger FOT increase is observed for HfSiO[sub2∙] with [Hf] 40% as compared to HfO[sub2∙]. In HfSiON, the desorbed H[sub2]O concentration is independent of [Hf]. Finally, a strong metal dependency on the EOT regrowth is observed. With ALD TiN, the EOT increase after thermal treatment is found to be independent of the degas condition at ∼0.2 nm. [ABSTRACT FROM AUTHOR]

This paper shows important improvements in charge pumping (CP) measurements on stacked high-k dielectrics, where the defects in high-k and SiO2 can be distinguished and estimated. The spatial profile of the interface traps and bulk traps is obtained by plotting the trap density as a function of the discharge time. Furthermore, the spectroscopic character of the base-level CP technique is demonstrated in HfSiON/SiO2 gate dielectrics by changing the applied pulse bias. It is found that when large pulse amplitude is applied to the gate, two bands appear superimposed on top of the usual base-level CP curve, suggesting the presence of two separate defect energy levels in the high-k dielectric. [ABSTRACT FROM AUTHOR]

Combinatorial methodology enables the generation of comprehensive and consistent data sets, compared with the "one-composition-at-a-time" approach. We demonstrate, for the first time, the combinatorial methodology applied to the work function (Φm) extraction for Ta1-xAlxNy alloys as metal gates on HfO2, for complementary metal-oxide-semiconductor applications, by automated measurement of over 2000 capacitor devices. Scanning X-ray microdiffraction indicates that a solid solution exists for the Ta1-xAlxNy libraries for 0.05 ≤ x ≤ 0.50. The equivalent oxide thickness maps offer a snapshot of gate stack thermal stability, which show that Ta1-xAlxNy alloys are stable up to 950 °C. The Φm of the Ta1-xAlxNy libraries can be tuned as a function of gate metal composition over a wide (0.05 ≤ x ≤ 0.50) composition range, as well as by annealing. We suggest that Ta0.9Al0.1N1.24 gate metal electrodes may be useful for p-channel metal-oxide-semiconductor applications. [ABSTRACT FROM AUTHOR]

A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability ΔVth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates ΔVth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of ΔVth is clarified. [ABSTRACT FROM AUTHOR]

A pFET threshold-voltage (Vt) reduction of about 200 mV is demonstrated by inserting a thin Al2O3 layer between the high-K dielectric and the TiN gate without noticeable degradation of other electrical properties. HfSiOx capped with 9 Å of Al2O3 obtains a low long-channel Vt of —0.37 V (the lowest among those with TiN gate), a high mobility of 59 cm2 ⁄V · s at 0.8 MV/cm (92% of universal value), a negligible equivalent. oxide-thickness (EOT) increase of 0.1 Å (compared to the uncapped reference), and a low Vt instability of 4.8 mV at 7 MV/cm. It also passes the ten-year negative-bias-temperature-instability (NBTI) lifetime specification with a gate overdrive of —0.7 V. This indicates that Al2O3 caps are beneficial to the pFET applications. In contrast, nitrogen incorporation in the Al2O3-capped HfSiOx is not favorable because it increases the Vt by 50—140 mV, degrades the mobility by 10%-22%, increases the EOT by 0.5—0.8 Å and the Vt instability by 5–13 mV, and reduces the NBTI lifetime by four to five orders of magnitude. Compared to postcap nitridation, posthigh-k nitridation results in more severe degradation of these properties by incorporating nitrogen closer to the Si/SiO2 interface. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) with HfCl4 as a precursor is widely used for HfO2 fabrication. Due to the nature of the precursor under study, i.e., HfCl4 and H2O, the presence of chlorine residues in the film due to insufficient hydrolysis is eminent. Obviously, the chlorine residue in the HfO2 film is suspected to affect the quality of the HfO2 film. In this paper, we reduced the concentration of chlorine residues by increasing the H2O oxidant pulse time in between the deposition cycles from 0.3 to 10 and 90s. Time-of-flight secondary ion mass spectrometry analysis shows that this decreases the chlorine concentration in the HfO2 film by more than one order of magnitude. However, time-dependent dielectric breakdown analysis shows that the lifetime remains quasi unaffected (within identical error bars) for the different injection cycles. Charge pumping analysis was done by varying both pulse frequency and amplitude to investigate the creation of defects, but negligible differences were observed. Therefore, we conclude that the presence of chlorine residues has no significant impact on the trap generation and reliability of ALD HfO2 layers, and this result corresponded with the mobility result. The experimental picture is confirmed with first-principle calculations that show that the presence of chlorine residues does not induce defect levels in the bandgap of HfO2. [ABSTRACT FROM AUTHOR]

The effects of source/drain activation thermal bud- get and premetallization degas conditions on interfacial re- growth, carrier mobility, and defect densities are examined for SiO2/HfO2/TaN stacks. We observe a correlation between the mobility degradation and the interfacial re-growth possible with the thermal budget employed. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-κ bulk, as detected by both pulsed current-voltage and charge-pumping measurements. Two junction activation processes have been applied: a conventional process (peak temperature of 1000 °C spike for t = 1 s) and a Solid Phase Epitaxial Re-growth (SPER) (peak temperature of 650 °C for t = 60 s). For 1000 °C spike-annealed films, where the highest SiO2/IL defect density is observed, the consequent mobility degradation is explained by a transition region between HfO2 and the IL which increases for high-temperature processing. [ABSTRACT FROM AUTHOR]

In this paper, an effective technique and methodology for the estimation of fixed charge components in high-k stacks was demonstrated by varying both the SiO2 and high-k dielectric thicknesses. The SiO2 thickness was scaled on a single wafer by uniformly changing the etch time of a thermally grown SiO2 layer across the wafer. This minimized wafer-to-wafer variations and enables acquisition of statistically significant datasets. Layers with different thickness of both the nitrided and non-nitrided hafnium-silicate layers were then grown on these wafers to estimate all the interfacial and bulk charge components. The reproducibility and validity of this technique were demonstrated, and this method was used to compare the fixed charge levels in Hf-silicates (HfSiO) and nitrided-Hf-silicate (HfSiON) layers. [ABSTRACT FROM AUTHOR]

Bi-Iayer gate stacks consisting of a HfO2 and an interfacial layer are fabricated by remote plasma oxidation (RPO) of Hf metal deposited on an Si substrate. Hf metal is fully oxidized by the RPO even at a temperature as low as 400 °C due to radical oxygens, leading to an improvement in the quality of HfO2 with less impact to the interfacial layer growth. An insufficient oxidation leads to a deterioration of mobility with increasing interface traps and positive bias temperature instability, which is likely caused by the oxygen vacancies acting as traps induced by the remaining Hf metal. The SiO2 -like interface improves the mobility with reduced interface states. Full oxidation and the controlled SiO2-like interface demonstrate RPO as a promising way for gate-stack optimization. [ABSTRACT FROM AUTHOR]

Dielectric relaxation currents in SiO2 /Al2O3 and SiO2 /HfO2 high-κ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-κ dielectric stacks. It is found that high-κ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-κ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO2/high-κ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO2/high-κ interface is a key requirement for high-κ dielectric stack application and reliability in MOS devices. [ABSTRACT FROM AUTHOR]

Extreme ultra-violet lithography (EUVL) is the leading-edge technology to produce advanced nanoelectronics. The further development of EUVL is heavily based on implementing the so-called high numerical aperture (NA) EUVL, which will enable even smaller pitches up to 8 nm half pitch (HP). In anticipation of this high NA technology, it is crucial to assess the readiness of the current resist materials for the high NA regime to comply with the demanding requirements of resolution, line-edge roughness, and sensitivity (RLS). The achievable tighter pitches require lower film thicknesses for both resist and underlying transfer layers. A concern that is tied to the thinning down is the potential change in resist properties and behavior due to the interaction with the underlayer. To increase the fundamental understanding of ultra-thin films for high NA EUVL, a method to investigate the interplay of reduced film thickness and different patterning-relevant underlayers is developed by looking at the glass transition temperature (Tg) of polymer-based resists. To minimize the ambiguity of the results due to resist additives (i.e., photoacid generator (PAG) and quencher), it was opted to move forward with polymer-only samples, the main component of the resist, at this stage of the investigation. By using dielectric response spectroscopy, the results obtained show that changing the protection group of the polymer, as well as altering the polymer film thickness impacts the dynamics of the polymer mobility, which can be assessed through the Tg of the system. Unexpectedly, changing the underlayer did not result in a clear change in the polymer mobility at the tested film thicknesses. [ABSTRACT FROM AUTHOR]

The density of hafnium oxide films grown by atomic layer deposition for high-κ gate dielectric applications was investigated for films with thickness in the nanometer range. The density, measured by combining the film thickness from transmission electron microscopy with the amount of hafnium deposited from Rutherford backscattering, decreased with decreasing film thickness. The dielectric constant of hafnium oxide remained constant with decreasing film thickness, however. The main reason for the decrease in the measured density seemed not to be a decrease in the inherent material density. Instead, the relative importance of interface roughness in the density measurement increased with decreasing film thickness. [ABSTRACT FROM AUTHOR]

The performance of modern chips is strongly related to the multi-layer interconnect structure that interfaces the semiconductor layer with the outside world. The resulting demand to continuously reduce the k-value of the dielectric in these interconnects creates multiple integration challenges and encourages the search for novel materials. Here we report a strategy for the integration of metal-organic frameworks (MOFs) as gap-filling low-k dielectrics in advanced on-chip interconnects. The method relies on the selective conversion of purpose-grown or native metal-oxide films on the metal interconnect lines into MOFs by exposure to organic linker vapor. The proposed strategy is validated for thin films of the zeolitic imidazolate frameworks ZIF-8 and ZIF-67, formed in 2-methylimidazole vapor from ALD ZnO and native CoOx, respectively. Both materials show a Young's modulus and dielectric constant comparable to state-of-the-art porous organosilica dielectrics. Moreover, the fast nucleation and volume expansion accompanying the oxide-to-MOF conversion enable uniform growth and gap-filling of narrow trenches, as demonstrated for 45 nm half-pitch fork-fork capacitors. Insulating materials combining a high mechanical stability, a low dielectric constant and the ability to completely fill narrow gaps are essential to fabricate interconnects for future high-performance chips. Here, the authors integrate zeolitic imidazolate frameworks as ultra-low-k dielectrics within a 90 nm pitch metallization layer via selective vapor-based conversion of metal oxide films. [ABSTRACT FROM AUTHOR]

Ultrathin lanthanide (Nd, Pr, Eu, Sm) oxide films with functional dielectric properties down to 3.3 nm thickness were deposited by aqueous chemical solution deposition (CSD) onto hydrophilic SiO2/Si substrates. Precursor solutions were prepared from the oxides via an intermediate, solid Ln(III)citrate. A film heat treatment scheme was derived from thermogravimetric analysis of the precursor gels, showing complete decomposition by 600 °C. Crystalline phase formation in the films depended on the lanthanide, annealing temperature, and citric acid content in the precursor. Through variation of the precursor concentration and number of deposited layers, thickness series of uniform films were obtained down to ~3 nm. The film uniformity was demonstrated both by atomic force microscopy and cross-section transmission electron microscopy. The lanthanide oxide films possessed good dielectric properties. It was concluded that aqueous CSD allows deposition of uniform ultrathin films and may be useful for the evaluation of new high-k candidate materials. [ABSTRACT FROM AUTHOR]

Assesses the compatibility of dielectric layers with conventional polysilicon gate electrodes. Use of standard processing equipment; Power capacity; Level of performance.

The article discusses the means of improving the workfunction control of metal gate electrodes. The author cites that the key challenge for applying metal gates for metal-oxide-semiconductor field-effect transistor is the choosing of a metal with suitable workfunction. The author also defines a novel route to workfunction control through the alteration of the interface polarization layer by cautious deposition of dielectric stack and metal gate, then, by a temperature treatment.