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Recently, multilevel inverter (MLI) is gaining immense popularity due to reduced total harmonic distortion, lower electromagnetic interference, and high quality output waveform in high/medium voltage applications. The reduced part count (RPC)-MLI has attracted the researchers by providing higher number of output voltage level with reduced part count as compared to the classical topologies (cascaded H-bridge, neutral point clamped, and flying capacitor). But the discussion over their suitability for particular application is not yet explored completely. In this paper, some of the recently proposed RPC-MLI topologies are reviewed and analysed. RPC-MLI topologies are compared on the basis of number of switches, driver circuits, diodes, standing/blocking voltage across the switches, and switching losses for grid interfacing application. These topologies are simulated here under the same load and input source condition using real time simulator. [ABSTRACT FROM AUTHOR]

This study presents a new multilevel inverter (MLI) with reduced devices, for low/medium- and high-voltage applications. The proposed MLI is evolved from existing cross-connected source-based multilevel inverter (CCS-MLI), results in reduced switches, driver circuits, diodes, and DC voltage sources when compared with the classical CHB, CCS-MLI, and other MLIs. Owing to reduced device numbers, the complexity, size, cost, and maintenance of the proposed topology are greatly reduced. The detailed analysis and working of the proposed topology is presented along with its comparison with classical, CCS-MLI, and other MLIs. Different algorithms are presented for selecting appropriate magnitudes of DC voltage sources to generate different voltage levels in the output. The proposed MLI is suitable for grid integration of renewable energy sources. The concept is presented through modelling and simulation in MATLAB/Simulation environment and validated through real-time simulator OPAL-RT (OP-4500). [ABSTRACT FROM AUTHOR]

In this paper, an improvisation of cross-connected sources based multilevel inverter (CCS-MLI) topology is presented in terms of maximization of levels. The proposed modified CCS-MLI will boost the output levels with the addition of one bidirectional switch in the existing CCS-MLI. The proposed modified topology lowers the switches number, diodes, gate drivers, dc power supplies, size, installation area and the cost of the system in comparison with conventional topologies and existing CCS-MLI. Working of the proposed topology is presented through a mathematical modelling and switching table. Finally, to confirm the effective performance of the proposed topology, simulation results by MATLAB/simulation and experimental results are given. [ABSTRACT FROM PUBLISHER]

Multilevel inverters (MLIs) have been developed to a matured level for generating high quality output voltage, used in numerous applications. Conventional MLIs has been received more attention due to their remarkable use in medium-voltage applications. But use of high number of part counts in conventional MLIs increase the intricacy of circuitry and controlling both results in high expenses and reduced reliability. Therefore, development of newer topologies is an active attention to reduce part count compared to the conventional MLIs. This paper presents an exhaustive review of recently proposed reduced part count MLIs for grid integration application on the basis of selection of components, comparative factors and their suitability. It is aimed at presenting a state of the art on configuration, working and their features to researchers, inventors, and application engineers dealing with multilevel inverters. [ABSTRACT FROM AUTHOR]

Multilevel inverter (MLI) is gaining rapid popularity in high/medium power applications due to low THD and high quality output waveform. Recently, the MLI topologies with reduced part count has attracted the researchers by offering higher number of output voltage level with reduced part count as compared to classical topologies (CHB, NPC and FC). It is observed that these recently proposed topologies are aimed to increase the output level with less number of components but the discussion over their suitability for a particular application is not yet explored completely. The main purpose of this paper is to provide an instructive review and analysis of existing MLIs with reduced part count. An exhaustive comparison of MLIs are assessed based on the number of switches, standing/blocking voltage across the switches, conduction losses, switching losses and cost. With the outcome of comparison results, suitable structure of MLI can be judged with reduced number of components and losses for given applications. [ABSTRACT FROM AUTHOR]

Reduced part count multilevel inverters (RPC-MLIs), an emerging technology for grid interfacing applications of renewable energy sources. RPC-MLIs overcome the limitations of conventional two-level and classical multilevel inverters (NPC, FC and CHB) by the use of reduced part counts for generation of same number of levels in the output. Focus of this paper is on to present review of the RPC-MLIs for researchers and engineers and classification of all the topologies. RPC-MLIs are compared considering its circuit complexity and performance. The comparison exposes advantages and disadvantages of topologies, as well as a wide spectrum for future research. This paper also draws the most potential topology in the field of grid integrated applications. Promising topology is simulated here under the same load and input source condition using real time simulator. [ABSTRACT FROM AUTHOR]

Multilevel inverters have created a new wave of interest in industry and research. While the classical topologies have proved to be a viable alternative in a wide range of high-power medium-voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the classical topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analyzed. The paper will serve as an introduction and an update to these topologies, both in terms of the qualitative and quantitative parameters. Also, it takes into account the challenges which arise when an attempt is made to reduce the device count. Based on a detailed comparison of these topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application. [ABSTRACT FROM AUTHOR]

This paper presents a multilevel inverter that has been conceptualized to reduce component count, particularly for a large number of output levels. It comprises floating input dc sources alternately connected in opposite polarities with one another through power switches. Each input dc level appears in the stepped load voltage either individually or in additive combinations with other input levels. This approach results in reduced number of power switches as compared to classical topologies. The working principle of the proposed topology is demonstrated with the help of a single-phase five-level inverter. The topology is investigated through simulations and validated experimentally on a laboratory prototype. An exhaustive comparison of the proposed topology is made against the classical cascaded H-bridge topology. [ABSTRACT FROM PUBLISHER]

As multilevel inverters are gaining increasing importance, newer topologies are being proposed to reduce part count for large number of levels in output voltage. A simplified five-level inverter has been recently reported in the literature to reduce component count. The topology comprises of floating input DC sources connected in opposite polarities through power switches. The structure requires lesser active switches as compared with conventional cascaded H-bridge topology with much reduced switching losses. Available literature present generalisation of the topology with symmetrical sources, but no investigations are made for equal load sharing and asymmetrical configurations. This study presents a comprehensive analysis of the aforementioned topology, referred to as cross-connected sources-based multilevel inverter (CCS-MLI). The topology is analysed for both symmetric and asymmetric source configurations. Also, a new algorithm for asymmetric source configuration suitable for CCS-MLI is proposed. A control scheme is also proposed for equal load sharing in five-level topology. Investigations are made for possibility of equal load sharing in higher level structures and fundamental frequency switching of switches bearing higher voltage stresses. Various concepts are verified with simulations and experimental studies. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a simple neutral point potential (NPP) regulator for a three-level diode-clamped inverter employing a sine-triangle regulator in conjunction with a closed-loop controller with reduced switching losses. The regulator principle is based on adding a continuous variable offset voltage which regulates the midpoint potential of the dc bus. The novelty of the proposed NPP regulator is in the determination of the magnitude of variable offset voltage based upon the average value, peak-to-peak amplitude, total harmonic distortions, and third harmonic content in NPP. Aside from maintaining dc-bus voltage balance, the proposed regulator leads to a significant reduction in the voltage distortion at the NP, resulting in the reduction of the required dc-bus capacitance. It also reduces the switching losses of the inverter by inserting the “no-switching” zone within each half cycle of the fundamental voltage wave. Analytical, computer simulation, and experimental results verifying the approach are presented in this paper for various load power factor angles. [ABSTRACT FROM AUTHOR]

Abstract: Recently multilevel inverters are gaining popularity due to reduced voltage stress across power switches and low total harmonic distortion (THD) output voltage waveform. However, device count increases with increased voltage levels. This paper presents a novel multilevel topology which is capable of obtaining all additive and subtractive combinations of input DC levels in the output waveform. Though all such levels can be obtained using the proposed topology, the actual number of levels depends on the DC source arrangement. A comparison is made between proposed topology and the classical multilevel topologies on the basis of device count and number of levels in the output voltage waveform. A detailed study of the proposed topology is presented through the example of a nine-level inverter. Appropriate modulation scheme is also presented. The proposed concept is analyzed through simulation studies and verified experimentally. [Copyright &y& Elsevier]

A new topology for multilevel DC-AC conversion is presented in this study. It consists of isolated symmetric input DC sources alternately connected in opposite polarities through power switches. The structure allows synthesis of multilevel waveform using reduced number of power switches as compared to the classical topologies. The working principle of the proposed topology is explained with the help of a single-phase five- level inverter. Simulation studies are carried out in MATLAB/Simulink environment and experimental validations are obtained on a laboratory prototype. An exhaustive comparison of the proposed topology against the classical cascaded H- bridge topology indicates reduction in number of power switches, losses, installation area and converter cost. [ABSTRACT FROM AUTHOR]

This paper presents a new topological structure for symmetrical cascaded multilevel inverters. The proposed circuit consists of cross-connected separate symmetrical DC sources which can generate number of levels equal to that of a cascaded H-bridge topology with reduced number of power switches. It is especially suitable for utility interfacing of renewable energy sources. It also offers the possibility of a transformer less and filter less operation. The working principle of the proposed topology is explained with the help of a single-phase five level inverter. Simulation results are obtained in matlab/simulink environment and are verified experimentally on a laboratory prototype. An exhaustive comparison of the proposed topology is made with the classical cascaded H-bridge topology, especially with the considerations of conduction losses and cost-effectiveness. The proposed topology results in the reduction of number of power switches, losses, installation area, and converter cost and thus can be implemented as an effective and efficient power electronic interface for renewable sources of energy with the utility grid. [ABSTRACT FROM AUTHOR]

Common mode voltage (CMV) generation is a major problem in switching power converter fed induction motor drive systems. CMV is the zero sequence voltage generated due to the switching action of power converters. Even a small magnitude of CMV with a high rate of change may circulate large bearing currents which may damage a machine's bearings and shorten its life. There are several methods of controlling CMV. This paper presents 3-level sinusoidal pulse width modulation based techniques to control the magnitude and rate of change of CMV in multilevel AC-DC-AC drive systems. Simulation and experimental investigations have been presented to validate the performance of proposed technique to control CMV in 3-level neutral point clamped inverter based AC-DC-AC system. [ABSTRACT FROM AUTHOR]