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We have been developing an SFQ shift register memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift register memory is composed of shift registers with non-destructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the memory system at high speed. The tested circuit is a 4-byte shift register file, where four kinds of wiring circuits are used between a decoder and shift registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the memory system. We have used the NEC 2.5 kA/cm2 Nb standard process and the CONNECT cell library. [Copyright &y& Elsevier]

We have designed and implemented an SFQ programmable clock generator (PCG), which can generate the variable number of SFQ pulses according to its internal state. The PCG is composed of an SFQ ring oscillator, a control circuit which counts up the number of SFQ pulses and stops the operation of the ring oscillator, and a decoder which defines the initial state of the control circuit. The PCG can generate the variable number of SFQ pulses ranging from 2 to 2N, where N is the number of T flip-flops in the control circuit. The oscillation frequency of the PCG is designed to be ranging from 6.2 to 18.8 GHz. In this study, we have implemented a PCG generating SFQ pulses ranging from 2 to 24 using a cell-based design methodology and confirmed its correct functionality. [Copyright &y& Elsevier]