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The operation of a capacitorless (1T) dynamic random access memory (DRAM) can be compromised if the storage region is located near metal–semiconductor junction in a reconfigurable field-effect transistor (RFET). Through subtle modifications, without affecting current drive, capacitance, and reconfigurable features, the present work showcases feasible 1T-DRAM operation in a RFET with an intentionally misaligned polarity gate. Analysis based on device physics and operation, highlights 1T-DRAM for standalone and embedded applications with impressive performance indicators: sense margin $\ge 6~\mu \text{A}/\mu \text{m}$ , retention time ≥16 ms (for embedded), and ≥64 ms (for standalone) at 85 °C, current ratio of ~104 along with a low write (~ 1 ns) and read (~ 2 ns) time. Guidelines in terms of scalability of total length and biases for implementing 1T-DRAM cell are presented. [ABSTRACT FROM AUTHOR]

This article reports on logic and memory functionality of vertically stacked bidirectional junctionless (BiJL) transistor, which can be operated as nMOS or pMOS depending on the biases applied. An inverter can be realized with a single BiJL transistor. If a complement of inputs is available, then NAND, NOR, and XOR logic can also be realized through a single BiJL transistor. The thickness of separation oxide between n-type and p-type films can be utilized to either achieve hysteresis or the absence of the same. Results provide insights into device physics, operation, and showcase new viewpoints for designing logic and memory devices with vertically stacked JL architecture, thus achieving the desired functionality with a lesser number of transistors. [ABSTRACT FROM AUTHOR]

This paper reports on the detection of hydrogen (H2) gas by utilizing a gate-all-around nanowire (NW) junctionless (JL) transistor as a sensor. The effects of temperature and pressure are considered in the transduction process through a change in gate workfunction of palladium (Pd) gate after exposure to $H_{2}$ gas. The analysis is performed through TCAD simulations, and an analytical model is developed in the subthreshold regime of device operation at a relatively low drain bias of 0.5 V. The performance of the NW JL transistor gas sensor is evaluated through the OFF-current-based sensitivity ($S_{I}$) and sensitivity based on threshold voltage shift ($S_{V}$). The analytical model developed for $S_{I}$ and $S_{V}$ shows a very good consistency with simulation data. The anomalous behavior of threshold voltage with temperature in the NW JL transistor under the influence of $H_{2}$ gas is analyzed in detail. This paper predominantly focuses on utilizing the NW JL transistor for low-power gas sensing, specifically at low pressures (10−15–10−10 torr), for temperatures ranging from 250 to 450 K. Insights into physical mechanisms within the device due to the transduction process are highlighted for optimum sensing. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

This paper reports on the suppression of single-transistor latch, an extreme condition of impact ionization (I.I.), in n-type double-gate germanium (Ge) junctionless (JL) transistors. It is shown that JL transistors can be latched to the on-state due to an increase in the I.I. generated power per unit volume with an increase in drain bias, film thickness, oxide thickness, and doping. Latch, being detrimental to switching, can be effectively suppressed by applying an appropriate negative (positive) back-gate bias for n-type (p-type) JL MOSFET. The independent gate operation with appropriate back bias allows the device to overcome latching and regain switching action with a subthreshold swing (${S}$ -swing) <10 mV/decade at room temperature. The work showcases the limit imposed on back bias due to an increase in off-state current due to band-to-band tunneling along with the utility of sidewall spacer to effectively suppress the same. We also show the tunability of hysteresis using back-gate bias. The work highlights a systematic methodology to eliminate single-transistor latch while preserving sub-60 mV/decade switching in Ge JL MOSFETs. [ABSTRACT FROM AUTHOR]

This paper reports on the potential benefits of a vertically stacked ${n}$ - and ${p}$ -type junctionless (JL) transistor physically decoupled through an intermediate oxide layer for dynamic memory application. The proposed topology enhances the retention time (RT) of capacitorless dynamic random access memory (1T-DRAM), with a significant improvement $(\sim \!\!\times 10^{3})$ compared with a conventional JL transistor with a doping (${N}_{\text{d}}$) of 1019 cm−3. The functionality of architecture as DRAM is based on physically decoupling the conduction region (top ${n}$ -type JL transistor) and storage region (bottom ${p}$ -type JL), while maintaining an electrostatic coupling between them. The charge stored in the ${p}$ -type JL determines RT, and also impacts the read currents, and thus, influences the sense margin of DRAM. Stacked JL (SJL) 1T-DRAM achieves a maximum RT of ~2.5 s for ${N}_{\text{d}} = 5 \times 10^{18}$ cm−3 and ~1 s for 1019 cm−3 with a gate length (${L}_{\text{g}}$) of 200 nm at 85 °C. Results demonstrate its functionality down to 20 nm. The enhanced DRAM metrics (better scalability and high RT) are attributed to optimal architecture due to the vertical stacking of ${n}$ - and ${p}$ -type regions. [ABSTRACT FROM AUTHOR]

We report a twin gate tunnel field effect transistor-based capacitorless dynamic memory with improved retention characteristics through well-calibrated simulations. The first front gate of the twin gate architecture regulates the read mechanism based on band-to-band tunneling whereas the second front gate creates and maintains a dedicated volume for the charge storage near the drain region. The profound well along with the optimized bias values aid to attain a retention time (RT) of $\sim 1.5$ s at 85 °C. Systematic analysis shows that the storage region can be scaled down to 50 nm with further improvement in RT by using an underlap region between drain and second gate. Optimally designed twin gate device exhibits an improved RT at higher temperature (125 °C). [ABSTRACT FROM PUBLISHER]

In this work, we analyze back bias induced steep and dynamic subthreshold swing in junctionless double gate transistors operated in the asymmetric mode. This impact ionization induced dynamic subthreshold swing is explained in terms of the ratio between minimum hole concentration and peak electron concentration, and the dynamic change in the location of the conduction channel with applied front gate voltage. The reason for the occurrence of impact ionization at sub-bandgap drain voltages in silicon junctionless transistors is also accounted for. The optimum junctionless transistor operating at a back gate bias of -0.9 V, achieves over 5 orders of change in drain current at a gate overdrive of 200mV and drain bias of 1V. These results for junctionless transistors are significantly better than those exhibited by silicon tunnel field effect transistors operating at the same drain bias. [ABSTRACT FROM AUTHOR]

Abstract: The performances of the junctionless nanowire transistor (JNT) are evaluated under high-performance (HP) ITRS device technical requirements for the 25nm technology node. The electrical characteristics of the devices are obtained from numerical simulations. The threshold voltage of JNT can be easily adjusted by changing different variable parameters such as fin width, fin thickness, doping concentration, gate oxide thickness and gate work function. The variation of threshold voltage with physical parameters is analyzed. The current drive is controlled by doping concentration and nanowire size. For gate length down to 25nm, a 30–40% increase in drain current is also reported by using a fin aspect ratio of 2 instead of 1. Additional source and drain implantation can be applied to improve the current drive. [Copyright &y& Elsevier]

This paper presents the effect of different elastic acoustic and inelastic optical electron–phonon interaction mechanisms on quantum transport and electrical characteristics of multigate silicon nanowire FETs. A 3-D quantum–mechanical device simulator based on the nonequilibrium Green's function formalism in the uncoupled mode space that can handle electron–phonon interactions has been developed to extract the physical parameters of the devices. The electron–phonon scattering has been treated by using the self-consistent Born approximation and deformation potential theory. Utilizing this simulator, we show that interaction of the carriers with optical phonons redistributes the energy and momentum of electrons in the transport direction, depending on the energy of the phonon. Optical phonons cause either a reduction of the electron density or an increase of the electron concentration in the channel region, depending on the phonon energy and coupling strength. Finally, we show that the critical length for carriers to get backscattered in the silicon nanowire is directly proportional to the phonon energy. [ABSTRACT FROM AUTHOR]

Abstract: In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DG devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut–off frequency (f T) and intrinsic voltage gain (A VO). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate–underlap DG MOSFETs. [Copyright &y& Elsevier]

Abstract: The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A VO) and cut-off frequency (f T) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25nm gate length SDE region engineered DG MOSFET operating at drain current of 10μA/μm, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g m), transconductance-to-current ratio (g m/I ds), Early voltage (V EA), output conductance (g ds) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. [Copyright &y& Elsevier]

In this work, we analyze hysteresis and bipolar effects in unipolar junctionless transistors. A change in subthreshold drain current by 5 orders of magnitude is demonstrated at a drain voltage of 2.25 V in silicon junctionless transistor. Contrary to the conventional theory, increasing gate oxide thickness results in (i) a reduction of subthreshold slope (S-slope) and (ii) an increase in drain current, due to bipolar effects. The high sensitivity to film thickness in junctionless devices will be most crucial factor in achieving steep transition from ON to OFF state. [ABSTRACT FROM AUTHOR]