Search

This study proposes a model of mobility and negative bias stress stability degradation mechanism of zinc oxynitride (ZnON) thin-film transistors (TFTs) with various anion compositions. The subgap density of states (DOS) for ZnON TFTs were extracted using monochromatic photonic capacitance–voltage measurement. The extracted subgap DOS indicated an additional nitrogen-related subgap peak was observed in ZnON TFTs with an excessive nitrogen condition, which might originate from a nitrogen divacancy formation. Furthermore, the shifted threshold voltage components after the bias stress test were quantitatively divided as subgap DOS and interface trapping.

In amorphous oxide semiconductors, hydrogen-related defects have been unable to be observed from the electrical characteristics of thin-film transistors (TFTs) in comparison to oxygen-related defects. Here, the hydrogen-related defect is observed as the Gaussian distributed density of states (DoS) in ${E}_{\text {C}}-{0.6}$ eV level by using the photoresponse of C-V characteristics in In-Ga-Zn-O (IGZO) TFTs. Coupled with X-ray photoelectron spectroscopy (XPS), it is identified as hydroxide ion (OH−), which both passivates oxygen vacancy defects and supplies the carriers as shallow donors. Furthermore, the evolution of DoS under positive bias stress and its origin are comparatively investigated for IGZO TFTs with three types of gate insulators (GIs), such as low-temperature atomic layered deposited Al2O3, thermally grown SiO2, and double-layered GIs.

In this letter, the effects of negative and positive bias stability with respect to the anion composition of Zn–O–N thin-film transistors were researched. In the positive bias stress tests, the threshold voltage shift was high for ZnON devices with high nitrogen composition. In contrast to this, the negative bias stress test results have smaller $\Delta ~\text{V}_{th}$ values when nitrogen composition in ZnON was low. This different degradation behavior of ZnON for thin-film transistors was analyzed by using the subgap density of states which were obtained from monochromatic photonic capacitance-voltage measurement.

In this work, the influence of anion composition on the photoresponse characteristics of zinc oxynitride thin film transistors is investigated and compared directly to conventional In-Ga-Zn-O TFTs. Increasing the ratio of N to (N+O) led to higher field effect mobility and improved subthreshold swing. The subgap density of states extracted by monochromatic photonic capacitance-voltage measurement indicated that the nitrogen-related defect states, such as nitrogen vacancies, increased with increasing nitrogen gas flow rate. Furthermore, the photoconductivity mechanism of ZnON TFTs is discussed in detail.

We proposed a physical model for ink-jet printed polymeric thin-film transistors (PTFTs) all over the sub- and above-threshold regions by using an effective carrier density. The nonlinearity under the low lateral electric field in the printed thiophene PTFTs was reproduced by applying the back-to-back Schottky diode model based on simple Poole–Frenkel (PF) mobility formalism. The analytical ${I}{-}\!{V}$ model supplemented with ${C}{-}\!{V}$ model in a single framework was also verified by successfully reproducing the measured characteristics of TFTs with three different thiophene polymeric channel materials. Additionally, we applied the physics-based analytical model on the inkjet-printed PTFT-based inverter and confirmed that the proposed models could predict the inverter circuit characteristics of the gain and static noise margin (SNM) based on the physical parameters.

The influence of anion composition on the electrical characteristics of amorphous zinc-oxynitride thin-film transitors (TFTs) is investigated and quantitatively modeled, with emphasis on the subgap density of states (DOS). As the ratio of N to (N + O) increases, the density of valence band tail states increases, followed by narrowing of the bandgap and a decrease in the density of conduction band tail states, which in turn is followed by either a higher field-effect mobility or a better subthreshold swing; each of these effects is explained. Furthermore, the anion composition dependence of the transconductance degradation at a high bias is analyzed on the basis of the proposed model. In addition, the effects of the N/(N + O) ratio on carrier density and field-effect mobility are quantitatively explained by the ionized nitrogen vacancy ( ${V}_{\text {N}}^{{1.3}+}$ ) model observed in shallow donor peak in the DOS and by the charge-controlled mobility model, respectively. Finally, the effect of nanocrystalline structure mixed with amorphous on transport properties is discussed.

Degradation on the current saturation of the output characteristics in amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors with the bottom-gate structure is investigated. As the drain-to-source voltage ( ${V}_{\textsf {DS}}$ ) increases at a fixed gate-to-source voltage ( ${V}_{\textsf {GS}}$ ), the current from drain to source ( ${I}_{\textsf {DS}}$ ) becomes nonsaturated and increases due to the mobility enhancement and ${I}_{\textsf {DS}}$ also decreases again due to the electron trapping into the gate insulator and/or an interface, which occurs mainly at the channel edge near a drain. Analysis is validated by using the pulsed ${I}_{\textsf {DS}}$ – ${V}_{\textsf {DS}}$ measurement. Nonsaturated current is attributed to the Joule heating-assisted mobility enhancement and the thermally activated electron trapping, which is the reason why the nonsaturation becomes more prominent as the IGZO active thin film becomes thinner. Furthermore, it is found that the rate of the increased ${I}_{\textsf {DS}}$ per increasing ${V}_{\textsf {DS}}$ gets higher as either the channel width ( ${W}$ ) increases or the channel length ( ${L}$ ) decreases; whereas, the rate of the decreased ${I}_{\textsf {DS}}$ per increasing ${V}_{\textsf {DS}}$ becomes higher as the device size, i.e., ${W}\times {L}$ , increases. The former is well correlated with Joule heating while the latter with the self-heating-assisted electron trapping due to a total heat accumulated in an active layer.

We propose a systematic calculation method for negative bias illumination stress (NBIS)-induced instabilities in amorphous InGaZnO thin-film transistors (TFTs). The proposed method is based on activation energy window (AEW) in subgap energy range, and it can reproduce the NBIS time evolution of ${I}$ – ${V}$ characteristics without long-term stress test. Furthermore, it quantitatively explains the effect of oxygen content on the NBIS instability. The AEW, which is employed for emulating the oxygen vacancy ionization, peroxide formation, and hole trapping, has the order of magnitude of 1016–1017 cm−3 for the bias stress of −20 V and the commercial LED backlight of 300 cd/m2. The proposed method is expected to play such an important role in the instability awareness of amorphous oxide TFTs.

In this study, we investigated how the structure and oxygen flow rate (OFR) during the sputter-deposition affects the photo-responses of amorphous indium-gallium-zinc-oxide (a-IGZO)-based photodetector devices. As the result of comparing three types of device structures with one another, which are a global Schottky diode, local Schottky diode, and thin-film transistor (TFT), the IGZO TFT with the gate pulse technique suppressing the persistent photoconductivity (PPC) is the most promising photodetector in terms of a high photo-sensitivity and uniform sensing characteristic. In order to analyze the IGZO TFT-based photodetectors more quantitatively, the time-evolution of sub-gap density-of-states (DOS) was directly observed under photo-illumination and consecutively during the PPC-compensating period with applying the gate pulse. It shows that the increased ionized oxygen vacancy (VO2+) defects under photo-illumination was fully recovered by the positive gate pulse and even overcompensated by additional electron trapping. Based on experimentally extracted sub-gap DOS, the origin on PPC was successfully decomposed into the hole trapping and the VO ionization. Although the VO ionization is enhanced in lower OFR (O-poor) device, the PPC becomes more severe in high OFR (O-rich) device because the hole trapping dominates the PPC in IGZO TFT under photo-illumination rather than the VO ionization and more abundant holes are trapped into gate insulator and/or interface in O-rich TFTs. Similarly, the electron trapping during the PPC-compensating period with applying the positive gate pulse becomes more prominent in O-rich TFTs. It is attributed to more hole/electron traps in the gate insulator and/or interface, which is associated with oxygen interstitials, or originates from the ion bombardment-related lower quality gate oxide in O-rich devices.

We report the effect of the oxygen content of the LaAlO3 layer on the synaptic behavior in the Pt/LaAlO3/Nb-doped SrTiO3 memristor for neuromorphic applications. As the oxygen-content decreases, the current becomes larger and the spike time-dependent plasticity (STDP) becomes less sensitive to the time difference between pre- and post-synaptic spike voltage. In addition, the conduction mechanism, which was found to be a combination of thermionic and Poole-Frenkel emissions, and the effect of oxygen content are explained in association with the oxygen vacancy in the LaAlO3 layer. The trade-off between large current and efficient STDP can be controlled by the oxygen content. Furthermore, the results of extracting the synaptic strength-based model parameters indicate that the Pt/LaAlO3/Nb-doped SrTiO3 shows the efficient STDP characteristics in comparison to previously reported memristor materials.

We propose a universal model for bias-stress (BS)-induced instability in the inkjet-printed carbon nanotube (CNT) networks used in field-effect transistors (FETs). By combining two experimental methods, i.e., a comparison between air and vacuum BS tests and interface trap extraction, BS instability is explained regardless of either the BS polarity or ambient condition, using a single platform constituted by four key factors: OH− adsorption/desorption followed by a change in carrier concentration, electron concentration in CNT channel corroborated with H2O/O2 molecules in ambient, charge trapping/detrapping, and interface trap generation. Under negative BS (NBS), the negative threshold voltage shift (ΔVT) is dominated by OH− desorption, which is followed by hole trapping in the interface and/or gate insulator. Under positive BS (PBS), the positive ΔVT is dominated by OH− adsorption, which is followed by electron trapping in the interface and/or gate insulator. This instability is compensated by interface trap extraction; PBS instability is slightly more complicated than NBS instability. Furthermore, our model is verified using device simulation, which gives insights on how much each mechanism contributes to BS instability. Our result is potentially useful for the design of highly stable CNT-based flexible circuits in the Internet of Things wearable healthcare era.

A physics-based compact model for phase-change random access memory (PcRAM) was proposed considering the ratio of vertical-to-lateral crystal growth rate (α), and it was incorporated into HSPICE via Verilog-A. The proposed model was verified using the experimental results taken from the 256 × 256 cross-point (X-point) PcRAM cell array with the Ge2Sb2Te5 20–22 nm ITRS technology node. The proposed compact model successfully reproduced the measured PcRAM cell resistance (RC) depending on the SET pulse width and amplitude after a background RESET, which is a challenging issue that holds back the X-point PcRAM as a promising candidate for a modern storage-class memory in perspective of the write latency and power consumption, without heavy computational burden while capturing the essence of physical meaning via the multidomain simulation which includes the threshold switching, electrical, thermal, and phase-change modules. The extracted α value was 1.55. Furthermore, it was found that the SET pulse-dependent abrupt/gradual change of RC is sensitive to α. This suggests that α should be carefully optimized for PCM-based neuromorphic applications

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) are investigated for a possible application to infrared (IR) photodetector through subgap density-of-states over the forbidden bandgap. The origin of the sub-bandgap( ${h}\nu photo-response in a-IGZO TFTs is due to optically pumped electrons from the photo-responsive subgap states ( ${E} _{C}$ - ${E} _{\textit {ph}}{ . Among the sub-bandgap lights, we investigate the reproducible IR photo-response in a-IGZO TFTs as a photodetector without the persistent photoconductivity (PPC) effect. In this letter, we characterize the IR photo-response mechanism through various optical and electrical measurements on the wavelength, optical power, bias-modulated quasi-Fermi level, and photo-responsive states. This result is expected to provide independent and/or integrated IR detector with transparent substrate combined with a-IGZO TFTs.

The transport and synaptic characteristics of the two-terminal Au/Ti/ amorphous Indium-Gallium-Zinc-Oxide (a-IGZO)/thin SiO2/p+-Si memristors based on the modulation of the Schottky barrier (SB) between the resistive switching (RS) oxide layer and the metal electrodes are investigated by modulating the oxygen content in the a-IGZO film with the emphasis on the mechanism that determines the boundary of the abrupt/gradual RS. It is found that a bimodal distribution of the effective SB height (&Phi, B) results from further reducing the top electrode voltage (VTE)-dependent Fermi-level (EF) followed by the generation of ionized oxygen vacancies (VO2+s). Based on the proposed model, the influences of the readout voltage, the oxygen content, the number of consecutive VTE sweeps on &Phi, B, and the memristor current are explained. In particular, the process of VO2+ generation followed by the &Phi, B lowering is gradual because increasing the VTE-dependent EF lowering followed by the VO2+ generation is self-limited by increasing the electron concentration-dependent EF heightening. Furthermore, we propose three operation regimes: the readout, the potentiation in gradual RS, and the abrupt RS. Our results prove that the Au/Ti/a-IGZO/SiO2/p+-Si memristors are promising for the monolithic integration of neuromorphic computing systems because the boundary between the gradual and abrupt RS can be controlled by modulating the SiO2 thickness and IGZO work function.

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

The memristor ratioed logic (MRL)-based NAND operation is demonstrated using a combination of two Ag/ $\gamma $ -Fe2O3 nanoparticles assembly/Pt memristors in series with one CMOS inverter. This letter finds the MRL operational frequency to be restricted due to an inconsistency between SET and RESET and by an imbalance of the resistance between the two memristors. It is also shown that optical tuning resistance is a promising technique for use in improving the operational frequency of the MRL operation. MRL-based NAND logic demonstrated in this letter manifests itself as a potential candidate for memristor-based logic compatible with CMOS digital/analog circuitry.

In this work, a SPICE compact model of indium-gallium-zinc oxide (IGZO) memristor in consideration of IGZO and electrode materials having non-quasi-statically updated Schottky barrier heights has been developed. In order for compact modeling of an analog memristor with higher accuracy, understanding of its switching characteristics and conduction behaviors needs to be preceded. It has been empirically revealed that they are dependent on metal species of the electrodes and processing approach. The switching characteristics are more weightedly determined by the interface between the switching layer and the metal with lower workfunction out of two electrode metals and interface status has been controlled by an Ar bombardment in this work. In order for identifying the conduction mechanism, a series of device simulations have been performed and the internal electric field distribution over the device structure has been closely investigated. It has been shown that the conduction behaviors are mainly determined by the thermionic emission taking place between Pd electrode and IGZO switching layer. For preparing the model parameters, along with the experimental results, transient measurement techniques have been cultivated at the same time, which has made possible to tell the difference between sets of model parameters obtained by theory and the techniques. In consequence, a highly reliable physics-based modeling for IGZO memristor has been developed through identification of switching and conduction mechanisms and extraction of the model parameters with the simultaneous help of Verilog-A equation build-up, which has demonstrated a plausible agreement with the measurement results.

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high VGS/low VDS and low VGS/high VDS stress conditions through incorporating a forward/reverse VGS sweep and a low/high VDS readout conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high VGS/low VDS stress is applied. On the other hand, when low VGS/high VDS stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high VGS/low VDS stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low VGS/high VDS stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive VGS/VDS stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

We quantitatively investigated instability mechanisms under simultaneous positive gate and drain bias stress (SPGDBS) in self-aligned top-gate amorphous indium-zinc-oxide thin-film transistors. After SPGDBS (VGS=13 V and VDS=13 V), the parallel shift of the transfer curve into a negative VGS direction and the increase of on current were observed. In order to quantitatively analyze mechanisms of the SPGDBS-induced negative shift of threshold voltage (DVT), we experimentally extracted the density-of-state, and then analyzed by comparing and combining measurement data and TCAD simulation. As results, 19% and 81% of DVT were taken to the donor-state creation and the hole trapping, respectively. This donor-state seems to be doubly ionized oxygen vacancy (VO 2+ ). In addition, it

We report a technique for separate extraction of extrinsic source/drain (S/D) resistances ( $R_{\mathrm {Se}}/R_{\mathrm {De}})$ and gate bias ( $V_{{\mathbf {GS}}})$ -dependent but channel length (L)-independent intrinsic source/drain ( $R_{\mathrm {Si}}/R_{\mathrm {Di}})$ resistances for the overlap region in MOSFETs. For extraction of the overlap length ( $L_{\mathrm {ov}})$ in the heavily doped S/D regions, an analytical capacitance model for the depletion region is employed with the gate-to-source and gate-to-drain capacitance–voltage ( $C_{{{G-S}}}$ , $C_{{{G-D}}})$ characteristics. After verifying the extracted overlap length through a 2-D technology computer-aided design simulation, we successfully extract $\mathrm{V}_{\mathrm {\mathbf {GS}}}$ -dependent $R_{\mathrm {\mathbf {Si}}}= 0.9{\sim }3.7~\Omega $ and $R_{\mathrm {\mathbf {Di}}}= 1.0{\sim }3.9~\Omega $ in an n-channel MOSFET with $W=140~\mu $ m and $L=0.35 ~\mu $ m. In addition, $V_{\mathrm {\mathbf {GS}}}$ - and $L$ -independent extrinsic S/D resistances are separately extracted to be $R_{\mathrm {Se}}=5.1~\Omega $ and $R_{\mathrm {De}}= 5.0~\Omega $ , respectively.

In this study, we implement an artificial synapse and neuron in a single platform by combining a silicon nanowire (SiNW) ion-sensitive field-effect transistor (ISFET), an indium-gallium-zinc-oxide (IGZO) memristor, and a voltage-controlled oscillator (VCO). The chemical and electrical operations of the synapse are emulated using the pH sensor operation of the ISFET and long-term potentiation/short-term plasticity of the IGZO memristor, respectively. The concentration of hydrogen ions in an electrolyte is successfully transformed via a VCO-based neuron into modulation of synaptic strength, i.e., the current of the memristor. It mimics the strength of the synaptic connection modulated by the concentration of the neurotransmitter. Thus, the chemical-electrical signal conversion in chemical synapses is clearly demonstrated. Furthermore, the proposed artificial platform can discriminate the chemical synapse from the electrical synapse and the path of the neuro-signal propagation and that of memorization/update of synaptic strength. This can potentially provide a new insight into the principles of brain-inspired computing that can overcome the bottleneck of the state-of-the-art von-Neumann computing systems.

Artificial synaptic potentiation and depression characteristics were demonstrated with Pt/CeO2/Pt devices exhibiting polarity-dependent analog memristive switching. The strong and sequential resistance change with its maximum to minimum ratio >105, imperatively essential for stable operation, as repeating voltage application, emulated the potentiation and depression motion of a synapse with variable synaptic weight. The synaptic weight change could be controlled by the amplitude, width, and number of repeated voltage pulses. The voltage polarity-dependent and asymmetric current–voltage characteristics and consequential resistance change are thought to be due to local inhomogeneity of electrical and physical states of CeO2 such as charging at interface states, valence changes of Ce cations, and so on. These results revealed that the CeO2 layer could be a promising material for analog memristive switching elements with strong resistance change, as an artificial synapse in neuromorphic systems.