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In this paper, temperature dependence of breakdown electrical field (Ebd) and time-to-failure (TTF) in AC TDDB for thick insulator film (300 nm) deposited by plasma process are discussed. In SiO2 film deposited using TEOS and O2 gases, increase of both Ebd and TTF beyond 100 °C is observed. On the other hand, in the SiO2 film and SiN film involving nitrogen, both Ebd and TTF decrease with increasing temperature. In order to explain this difference, we focused on the type of conductivity and introduced de-trapped effect by thermal energy. And we proposed a simple model to explain the temperature dependence of those AC TDDB results. In the SiO2 film deposited using TEOS and O2, the temperature dependence of number of trapped carrier is smaller because the conductivity type is the FN tunnelling, while the number of de-trapped carrier significantly increases with temperature and the TTF beyond 100 °C becomes longer. In these films involving nitrogen, the de-trapped effect is negligible because the number of trapped carrier exponentially increases with temperature because of Poole-Frenkel conductivity.

Unified transient and frequency domain noise simulation of random telegraph noise and flicker noise is conducted using a multiphonon-assisted model that considers tunneling probabilities and energy transitions of discretized traps in the gate insulator of MOSFETs. The proposed model is able to concurrently represent the dynamic behavior of electron and hole trapping and detrapping via interactions with both the Si substrate and Poly-Si gate. The model is implemented in a 3-D device simulator to examine the effect of device structure and bias conditions. The conventional analytical model does not precisely estimate the noise powers in short-channel MOSFETs due to the nonuniform trapped charge effect. The high trap density near the shallow trap isolation edges is predicted quantitatively by comparing the measured data with the simulated data. In conclusion, we confirm the validity of the developed unified simulator and its usefulness for gaining insights into trap sites and noise reduction engineering.

This paper presents the theoretical formulation of a lithographical bending control (LBC) method that uses lithographical degrees of freedom to control the bending of a multilayered beam. LBC is applied to a piezoelectric actuator that uses PZT as the piezoelectric material. The theoretical model is compared with measurements using a weakly fixed bridge structure suited for curvature measurement.

Frequency dependent properties of accumulation-mode MOS varactors, which are key elements in many RF circuits, are dominated by Non-Quasi-Static (NQS) effects in the carrier transport. The circuit performances containing MOS varactors can hardly be reproduced without considering the NQS effect in MOS-varactor models. For the LC-VCO circuit as an example it is verified that frequency-tuning range and oscillation amplitude can be overestimated by over 20% and more than a factor 2, respectively, without inclusion of the NQS effect.

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current-voltage characteristics

SUMMARY A systematic experimental and modeling study is reported, which characterizes the low-frequency noise spectrum of 100 nmMOSFETs accurately. Two kinds of measured spectra are observed: 1/f and non-1/f spectra. The non-1/f spectrum is analysed by forward and backward measurements with exchanged source and drain, and shown to be due to a randomly distributed inhomogeneity of the trap density along the channel and within the gate oxide. By averaging the spectra of identical MOSFETs on a wafer the measured non-1/f noise spectra reduce to a 1/f characteristics. On the basis of these measurement data a noise model for circuit simulation is developed, which reproduces the low-frequency noise spectrum with a single model parameter for all gate lengths and under any bias conditions.

Channel noise enhancement due to MOSFET scaling and its influence on phase noise estimation of fully integrated VCO have been studied. The channel noise of MOSFET increases due to the hot electron effect of small geometry MOSFET is obvious. The channel noise coefficient, γ, of NMOS is 3.5 for 40-nm gate length, 2.0 for 90-nm gate length in spite of being ⅔ for long channels MOSFET. Simultaneously, calculation of phase noise of fully integrated VCO shows large difference using γ=⅔ because the part of noise performance of VCO gain-cell depends on channel noise of MOSFET. Calculated phase noise showed good agreement with measured data when the optimum value of channel noise of MOSFET was adopted. Copyright © 2005 John Wiley & Sons, Ltd.

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs with 1.5 nm gate oxides. This is the highest value ever obtained for p-channel Si MOSFETs at room temperature. Further, it was demonstrated that more than 100 GHz of cutoff frequency is realized both for n- and p-MOSFETs. Thus, using [110] substrates results in a better balance for n- and p-MOS performances. The SiO/sub 2/ film and SiO/sub 2//Si interface qualities on [110] substrates were also investigated. In this experiment, it was found that direct-tunneling gate leakage current and initial 1/f noise of MOSFETs on [110] substrates are larger than those on [100] substrates. The reliability regarding Negative Bias Temperature Instability (NBTI) for p-MOSFETs on [110] substrates was also inferior to that for [100] MOSFETs. However, with a high-k insulator or improvement of the SiO/sub 2/ film quality, high mobility of p-MOSFETs on [110] substrates will have a potential not only for digital applications but also for new RF analog circuits under low supply voltage.

The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a [111] surface-oriented Si substrate were investigated and compared with those on a [100] substrate for the first time. It was confirmed that low field mobility of n-MOSFETs on the [111] substrate is smaller than that on the [100] substrate and that of p-MOSFETs on [111] is larger than that on [100] until the direct-tunneling gate oxide regime. It has been found that most of the electrical properties of MOSFETs, with the notable exception of mobility, become almost identical for [100] and [111] substrates when the oxide thickness is reduced to less than 2.0 nm. Some of the properties are quite different between the two substrates for the thicker oxide case. It has been found that the reliability of hot carrier injection and time-dependent dielectric breakdown (TDDB) of the oxides and MOSFETs on the [111] substrate is slightly better than that on the [100] substrate. In addition, the characteristics and reliability of oxides and MOSFETs on a wafer tilted 4/spl deg/ from [100] axis were investigated. It was found that there are few differences in the mobility between [100] and [100] 4/spl deg/ off substrates for both n- and p-MOSFET cases. The reliability of oxides or MOSFETs on the wafer was identical to that on normal [100] substrate. These results suggest that ultrathin gate oxide MOSFETs on Si surfaces with various orientations are likely to have practical applications. This is good news for possible future new structures of MOSFETs such as vertical or three-dimensional (3-D) MOSFETs.

Salicide is one of the indispensable techniques for high-performance logic devices and its importance increases as the device dimensions become small towards sub-100 nm and hence, the source/drain sheet resistance becomes large. TiSi2 used popularly as the silicide material has been eventually replaced by CoSi2, because of its relatively stable nature during the salicide process. For sub-100-nm technology node, CoSi2 is expected to be further replaced by NiSi. NiSi has several advantages over TiSi2 and CoSi2 for the ultra-small CMOS process. They are (1) low temperature silicidation process, (2) low silicon consumption, (3) no bridging failure property, (4) smaller mechanical stress, (5) no adverse narrow line effect on sheet resistance, (6) smaller contact resistance for both n- and p-Si, and (7) higher activation rate of B for SiGe poly gate electrode. In this paper, NiSi salicide technology is explained.

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO/sub 2/-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated.

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO/sub 2/ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-/spl mu/m and 0.06-/spl mu/m gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-/spl mu/m gate length pMOSFETs using 1.5-nm gate SiO/sub 2/ for the first time. The normal oscillations of the 1.5-nm gate SiO/sub 2/ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-/spl mu/m gate length CMOS in terms of high-frequency, high-speed operation.

Hot-carrier degradation on electrical characteristics of MOSFETs in the direct-tunneling regime of the gate oxide was investigated under a wide range of conditions, namely stress bias, oxide thickness, gate length, and channel-type dependence. It was confirmed that the transconductance degradation of n-MOSFETs with thinner gate oxides is smaller than that of thicker gate oxide MOSFETs, in spite of larger gate direct-tunneling leakage current and larger hot-carrier generation. For p-MOSFETs, little degradation was observed under all conditions of stress bias, oxide thickness, and gate length.

A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing the N/sup -/ extension impurity concentration-which determines the source-drain breakdown voltage (V/sub dss/)-and thinning the gate oxide-which determines the TDDB between gate and drain. Additionally, in order to reduce gate resistance, the Co-salicide process is adopted instead of metal gates. With salicide gates, a 0.2 /spl mu/m gate length is easily achieved by poly Si RIE etching, while if metal gates were chosen, the metal film itself would have to be etched by RIE and it would be difficult to achieve such a small gate length. Although the resistance of a Co-salicided gate is higher than that of metal gate, there is no evidence of a difference in power-added efficiency when the finger length is below 100 /spl mu/m. It is demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve a high power-added efficiency of more than 50% in 2 GHz RF operation with an adequate breakdown voltage (V/sub dss/). In particular, an efficiency of more than 50% was confirmed at the very low supply voltage of 1.0 V, as well as at higher supply voltages such as 2 V and 3 V. Small gate length Co-salicided Si-MOSFETs are a good candidate for low-voltage, high-efficiency RF power circuits operating in the 2 GHz range.

We describe the relationship between the sheet resistance of Co-silicided poly-Si and various doping elements. The surface condition of the poly-Si before Co sputtering plays an important role in suppressing the "narrow line effect," in which the silicide sheet resistance degrades as the gate length decreases. Si-O and Si-C bonding takes place in the gate poly-Si during RIE processing for gate side-wall formation when there is no CVD SiO/sub 2/ gate cap. This leads to the sheet resistance degradation of CoS/sub 2/ when the gate length is reduced. The degradation becomes less severe as the weight of the ions implanted during gate poly-Si doping increases, because the bonding is inhibited by heavier ions. The best way to suppress this degradation, however, is to prevent exposure of gate poly-Si surface by implementing a CVD SiO/sub 2/ cap during gate side-wall formation. When this is done, the sheet resistance degradation does not occur even when the gate length is 0.1 /spl mu/m for all types of implanted ions. We also observed thermal stability of the sheet resistance up to 1000/spl deg/C. That can be improved, as well as narrow line effect, by using this cap process. However, the thermal stability of gate oxide TDDB depends on the type of ion implantation. The temperature at which degradation of TDDB begins rises as the weight of the implanted ions increased. This degradation depends on the grain size, and grains increase in size as the weight increases. The highest temperature before the onset of TDDB degradation is seen with in-situ phosphorus-doped n/sup +/ polysilicon, because the grain size is greatest in this case.

A self-Aligned Doped Channel (SADC) is proposed and investigated for the first time. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate; hence the doping region is fully self-aligned to the gate, and the junction capacitance can be reduced. In addition, the implantation damage in the channel is reduced. We obtained 0.25 μm gate length nMOSFETs with low noise and low power consumption by using the SADC structure. Hence, this structure is attractive for small geometry RF CMOS devices.

A new process for a counter-doped region suitable for a 0.15 μm (gate length) buried channel (BC) pMOSFET is presented. At present serious short-channel effects of BC p-MOSFETs are recognized broadly as prohibitive for application at 0.1 μm. In order to realize 0.15 μm BC pMOSFETs, we propose a new process step, making use of a boron solid phase diffused channel (SPDC) from a Boron-doped silicate glass (BSG) to form an extremely shallow counter-doped region, which enables suppression of short-channel effects. Devices fabricated in this way exhibit good short-channel behavior at 0.15 μm gate length and, additionally, provide an excellent current driving-ability. Threshold voltage control is easy by optimizing the diffusion condition. We propose SPDC as a suitable process applicable to 0.2–0.1 μm BC p-MOSFET.

An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750/spl deg/C, the film quality is as good as the bulk silicon because high pre-heating temperature (940/spl deg/C for 30 s) is used in H/sub 2/ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ values than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications.

A silicided silicon-sidewall source and drain (S/sup 4/D) structure is proposed for sub-0.1-/spl mu/m devices. The merit of the S/sup 4/D structure is that the series resistance of the source and drain is significantly reduced since the silicide layer is attached very close to the gate electrode and the silicon sidewall can be doped very highly. Thus, very high drain current drive can be expected, Another advantage of this structure is that the source and drain extensions are produced by the solid-phase diffusion of boron from the highly doped silicon-sidewall. Thus, shallow extensions with very high doping can be realized. A 75-nm gate length pMOSFET fabricated with this structure is shown to exhibit excellent electrical characteristics.

Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 /spl mu/m/spl times/0.75 /spl mu/m, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n/sup +/ polysilicon gates subjected to RTA at 1050/spl deg/C for 20 s and furnace annealing at 850/spl deg/C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications.

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g/sub m/ of n-MOSFET with 40-nm epitaxial Si for 0.10-/spl mu/m gate length was 630 mS/mm at V/sub d/-1.5 V, and the drain current was 0.77 mA//spl mu/m. This g/sub m/ value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFET's are useful for future high-speed ULSI devices.

Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption. In this paper, a 0.15-/spl mu/m RF CMOS technology compatible with logic CMOS for low-voltage operation is described. Because the fabrication process is the same as the high-speed logic CMOS, manufacturability of this technology is excellent. Some of the passive elements can be integrated without changing the process and others can be integrated with the addition of a few optional processes. Mixed RF and logic CMOS devices in a one-chip LSI can be realized with relatively low cost. Excellent high-frequency characteristics of small geometry silicon MOSFETs with low-power supply voltage are demonstrated. Cutoff frequency of 42 GHz of n-MOSFETs, which is almost the same level at that of general high-performance silicon bipolar transistors, was obtained. N-MOSFET's maintained enough high cutoff frequency of 32 GHz even at extremely low supply voltage of 0.5 V. Moreover, it was confirmed that degradation of minimum noise figure for deep submicron MOSFETs with 0.5 V operation is sufficiently small compared with 2.0 V operation. These excellent high-frequency characteristics of small geometry silicon MOSFETs under low-voltage operation are suitable for mobile telecommunications applications.

We analyze the linearity of metal oxide semiconductor field effect transistors (MOSFETs) at radio frequency switching using the conventional extraction method of IP3, measured harmonic distortion (HD), and a surface-potential-based MOSFET model for circuit-simulation. The applicability of the conventional extraction method of IP3 at low frequency to represent IP3 at high frequency is also investigated. At low frequency, measured HD characteristics and extracted IP3 values correspond to the prediction by the model which adopts the quasistatic approximation, i.e., instantaneous carrier response is assumed. Beyond half of the cutoff frequency, the carrier response delay enhances the MOSFET nonlinearity, which is manifested by a decreased first order harmonic and a pronounced curvature of the third order harmonic. Consequently, the conventional extraction method of IP3 value from the intersection point of linearly extrapolated first and third harmonics becomes unreliable

The ability to operate 1.5 nm direct-tunneling gate oxide MOSFETs at low power and high speed with a low supply voltage in the 0.5 V range is investigated. We extrapolate the performance of current high-end MPUs assuming that conventional 0.4 μm MOSFETs are replaced by such direct-tunneling gate oxide MOSFETs. A simple estimate shows that the high current drive of direct-tunneling gate oxide MOSFETs may lead to MPUs which operate at frequencies several times higher than today's, while consuming several times less power.

A silicided silicon-sidewall source and drain (S/sup 4/D) nMOSFET is demonstrated and its hot carrier reliability is investigated for the first time. This S/sup 4/D nMOSFET exhibited high drain current and well-suppressed short channel effects concurrently. In spite of the impact ionization rate issue, the S/sup 4/D structure offers a major improvement in current and transconductance degradations as compared with the LDD structure. The mechanism of the improved hot carrier reliability is explained using a two-dimensional (2-D) simulation.

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 /spl mu/m, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA//spl mu/m and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 /spl mu/m at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used.

The reduction of gate length improves the performance of a MOSFET. However, this is difficult to do when the gate length is less than 0.1 μm for numerous reasons. This paper reports the results of improvement of the MOSFET performance employing various means. It was found that the current drive was only 30 percent higher with a gate length of 40 nm than with a gate length of 0.1 μm. Even when the gate oxide was 1.5 nm, which is half the oxide thickness for a direct tunneling leakage limit, it was found that the MOSFETs operate normally and the current drive was 1.6 times higher than when the gate oxide was 3 nm, because of the increase of gate capacitance. When a low-doped thin Si epitaxial layer was used as the intrinsic channel, the channel drive was improved by 20 percent because of higher carrier mobility, compared with the current-driving efficiency of a MOSFET formed by bulk material. The problem of source drain parasitic resistance increase in small-geometry MOSFETs was solved by using a novel device structure, i.e., S4D. Using this new structure, the parasitic resistance was reduced by one order of magnitude. Combining the aforementioned techniques, the current-driving efficiency could be improved further even when the gate length is in the sub-0.1 μm region.

A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n/sup +/- and p/sup +/-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600/spl deg/C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at the NiSi-Si interface is minimal, and a high dopant concentration is achieved at the silicide-silicon interface, thus contributing to low contact resistance. This NiSi technology was used in the experimental fabrication of deep-sub-micrometer CMOS structures; the current drivability of both n- and p-MOSFET's was higher than with the conventional titanium salicide process, and ring oscillator constructed with the new MOSFET's also operated at higher speed. >

A systematic investigation of the influences of high substrate doping on the hot carrier characteristics of small geometry n-MOSFETs down to 0.1 /spl mu/m has been carried out. Results indicate that the dependence of substrate current and impact ionization rate on substrate impurity concentration is reversed in long channel and short channel devices. In the long channel case, both increase with rising substrate impurity concentration, while they decrease in the case of short channel devices. An explanation for this phenomenon based on the lucky electron model has been developed. The dependence of other characteristics on impurity concentration has also been studied. The dependence of off-leakage current has been found to fall as the gate oxide is reduced in thickness. Regarding the dependence of hot carrier degradations, the degradation of drain currents becomes smaller as the substrate impurity concentration increases in the case of short channel devices. Further, in the extremely high impurity doping region, a new hot carrier degradation mode was found, in which the maximum transconductance values of n-MOSFETs increase after hot carrier stress. This new degradation mode can be explained in terms of effective channel length shortening caused by electron trapping. >

Forty nm gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFETs, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 nm gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 nm source and drain junctions. The resulting 40 mm gate length n-MOSFETs operate quite normally at room temperature. Using these n-MOSFETs, we investigated short channel effects and current drivability in the 40 nm region at room temperature. We have also investigated hot-carrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 nm, and that both impact ionization rate and substrate current fall significantly as V/sub d/ falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 mm region if V/sub d/ is less than or equal to 1.5 V. >

A contact plug technique employing selective nickel silicidation of polysilicon with a titanium nitride barrier layer has been developed. This technique provides a contact resistance equal to that of an unplugged metal contact, while also realizing the flatness of a polysilicon plug over contact regions. Using this technique, a completely silicided plug for both shallow and deep contact holes can be achieved at the same time. The structure of the plug was analyzed using TEM photography, EDX, and electro-diffraction measurements, and the silicidation stopping ability of the TiN layer was confirmed. The low leakage current of junction diodes and lack of transistor characteristic degradation when using the Ni silicided plug are demonstrations of the integrity of this technique. The results indicate that this technology is suitable for deep-submicrometer ULSIs. >

This special section contains a representative selection of papers presented at the 2010 International Conference on Microelectronic Test Structures (ICMTS).

A high-speed 0.15 μm single-gate Co salicide CMOS technology has been demonstrated, which suppresses short channel effects in 0.15 μm buried channel pMOSFETs by optimizing the fabrication conditions of their extension region. An unloaded CMOS inverter ring-oscillator delay of 19.8 ps has been obtained. At 0.12 μm gate length, 11.4 ps gate delay was observed.