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In this article, an output-capacitorless low-dropout (OCL-LDO) regulator that features low-power, small-transient-spike, and process-temperature (PT)-aware design for transient sustainability is presented. The circuit architecture is based on the improved PT-aware current source for keeping stable bandwidth and the proposed PT-aware transistor biasing network in conjunction of dual fast local feedback (DFLF) loops in a single power transistor stage to yield both enhanced and sustained transient metrics under a sub-1-V supply. Fabricated in 40-nm CMOS technology, the regulator can deliver a full-load current of 100 mA at a 100-pF load under a 0.75-V supply. From the measured results of 12 samples, it consumes an average quiescent power of 19.5 $\mu \text{W}$ and quiescent current of 26 $\mu \text{A}$ . It displays an average settling time of 414 ns for a full-load current of 100 mA at room temperature. The average load transient voltage spike is 23.9 mV and small when compared to the reported works at a similar level of load current. Finally, the process corner simulations at different temperatures together with the 12 measured samples at temperature corners have validated the sustainability of transient metrics.

A new biasing scheme is proposed for transistors used in power-amplifier applications. In the proposed biasing scheme, a constant current source is used as the power supply for the transistor’s output terminal. A whole new family of amplifier classes can be defined using this biasing scheme. Analytical equations are obtained and verified for current and voltage waveforms of a current-biased transistor for both resistive and tuned load impedances. Using the proposed current biasing scheme, the transistor presents completely different behaviors compared with the conventional voltage biasing scheme. These properties can be utilized for new design concepts and can provide new possibilities in the future designs and applications. Some of the differences between current-biased and voltage-biased amplifiers are discussed. One of the different behaviors shown by the current-biased transistor amplifiers is the reversed load modulation. Using this property of the current-biased amplifiers, a reversed modulation dual branch (RMDB) amplifier structure is proposed for ultra-wideband high efficiency at power back-off. Due to the reversed load modulation of current-biased transistors, a multibranch amplifier can be implemented to obtain high efficiency at power back-off without the need for an impedance inverter at the output of the current-biased amplifier. By using the proposed amplifier structure, a wideband RMDB amplifier was fabricated and tested exhibiting higher than 37% efficiency for long-term evolution (LTE) signals in 0.8–2.2-GHz bandwidth, which is equivalent to 93% fractional bandwidth.

An $E$ -band (71–86-GHz) bidirectional transceiver is presented in this paper. The time-division duplex architecture avoids transmit (TX)/receive (RX) switches through the use of transistor biasing in the signal path to minimize high-frequency loss. The low-noise amplifier (LNA) and power amplifier (PA) are combined into a wideband PA/LNA circuit, which alleviates the parasitic loading of each circuit through a wideband power combiner. The bidirectional transceiver circuit is implemented in 90-nm SiGe BiCMOS process. In TX mode, the bidirectional transceiver transmits a maximum saturated power of 11 dBm at 78 GHz with a 3-dB bandwidth from 71 to 86 GHz. In RX mode, the maximum 30.6-dB conversion gain and the minimum 6.6-dB noise figure are measured at 73 GHz. The whole RF frontend chip consumes 350.2- and 137.7-mW dc power in TX and RX modes, respectively, including all the RF, IF, and local oscillator amplifiers. The overall chip size is $1.5~\text {mm}\times 0.9$ mm including pads.

The performance of portable ultrasound systems is affected by the excessive heat generated by amplifiers, thereby reducing the sensitivity and resolution of the transducer devices used in ultrasound systems. Therefore, the amplifier needs to generate low amounts of heat to stabilize portable ultrasound systems. To properly control the amplifier, the related bias circuit must provide proper DC bias voltages for long time periods in ultrasound systems. To this end, a stacked transistor bias circuit was proposed to achieve a relatively constant amplifier performance irrespective of temperature variance without any cooling systems as the portable ultrasound system structure is limited. To prove the proposed concept, the performance of the gain and DC current consumption at different experimental times was measured and compared to a developed class-B amplifier with different bias circuits. The amplifier with the stacked transistor bias circuit outperformed with regard to the gain and DC current variance versus time (&minus, 0.72 dB and 0.065 A, respectively) compared to the amplifier with a typical resistor divider bias circuit (&minus, 5.27 dB and 0.237 A, respectively) after a certain time (5 min). Consequently, the proposed stacked transistor bias circuit is a useful electronic device for portable ultrasound systems with limited structure sizes because of its relatively low gain and DC current variance with respect to time.

In this brief, we propose a novel bipolar junction transistor-based I-MOS, called the bipolar I-MOS, to reduce the operating voltage of the I-MOS using the transistor gain action. Using 2-D simulations, we demonstrate that the proposed bipolar I-MOS exhibits a low operating voltage ( $\sim 2.8$ V), which is $\sim 60$ % lower than that of the corresponding p-i-n I-MOS, and also a steep subthreshold slope of 6.25 mV/decade. In the bipolar I-MOS, since the avalanche-generated carriers do not pass through the channel region under the gate, it is expected to have a higher reliability compared with the p-i-n I-MOS. Therefore, the bipolar I-MOS could be a promising candidate for near ideal switching applications.

A bidirectional low-noise amplifier (LNA) is presented in this letter. By using transistor bias control and low-loss coplanar waveguide structures with defected ground shield as both interconnect traces and distributed passives, the proposed two-port bidirectional amplifier achieves a measured performance close to the stand-alone LNA from 54 to 65 GHz. The design is fabricated in a 0.18- $\mu \text{m}$ SiGe BiCMOS process consuming a maximum 10.6-mA current from a 1.8-V supply voltage and occupies a 0.85-mm2 core die area.

This book, Electronic Devices and Circuit Application, is the first of four books of a larger work, Fundamentals of Electronics. It is comprised of four chapters describing the basic operation of each of the four fundamental building blocks of modern electronics: operational amplifiers, semiconductor diodes, bipolar junction transistors, and field effect transistors. Attention is focused on the reader obtaining a clear understanding of each of the devices when it is operated in equilibrium. Ideas fundamental to the study of electronic circuits are also developed in the book at a basic level to lessen the possibility of misunderstandings at a higher level. The difference between linear and non-linear operation is explored through the use of a variety of circuit examples including amplifiers constructed with operational amplifiers as the fundamental component and elementary digital logic gates constructed with various transistor types. Fundamentals of Electronics has been designed primarily for use in an upper division course in electronics for electrical engineering students. Typically such a course spans a full academic years consisting of two semesters or three quarters. As such, Electronic Devices and Circuit Applications, and the following two books, Amplifiers: Analysis and Design and Active Filters and Amplifier Frequency Response, form an appropriate body of material for such a course. Secondary applications include the use in a one-semester electronics course for engineers or as a reference for practicing engineers.

For application in radar and communication systems operating in the frequency range around 250 GHz, a power amplifier (PA) millimeter-wave monolithic integrated circuit (MMIC) has been developed. The amplifier makes use of a novel coupler approach allowing for in-phase and equal-magnitude distribution of an incoming signal to four parallel output ports. This is possible due to a subtle use of grounded coplanar waveguide and air-bridge microstrip transmission lines, providing different propagation constants. With a size of quarter-wavelength, the coupler is very compact and is the key to the presented PA topology. The amplifier exploits the virtual open occurring due to the identical signals for transistor biasing and matching. The amplifier topology is applied to develop an amplifier MMIC. When biased for maximum gain, it shows a 17-GHz 3-dB bandwidth around its center frequency at 248 GHz with a maximum gain of 32.8 dB. When biased for maximum output power, it provides an output power of 10 and 8.5 dBm at 250 and 270 GHz, respectively. At 250 GHz, it demonstrates a state-of-the-art power density of 125 mW/mm. Due to the amplifier topology, the MMIC is very compact $({\hbox{1.25}}\times {\hbox{0.75}}~{\hbox{mm}}^{2})$ .

This article describes the detailed development of a large-signal transistor model for a microwave power heterojunction bipolar transistor (HBT). Based on the neurospacemapping (Neuro-SM) technique, this model uses neural networks to map a coarse model space represented by the existing model simulations onto the fine model space represented by device measurements. This article tied for first place in the Microwave Transistor Modeling Student Design Competition at the 2014 IEEE International Microwave Symposium (IMS2014) held in Tampa, Florida.

Recently published reports suggest that symmetric lateral bipolar transistors on semiconductor-on-insulator (SOI) is CMOS compatible in fabrication process, and can be much denser than CMOS due to their much larger (5-10× larger) drive-current capability. When used in traditional bipolar circuits, SOI bipolar offers much lower power dissipation and/or much higher maximum speed. With both NPN and PNP devices of comparable characteristics, SOI lateral bipolar suggests the possibility of complementary bipolar (CBipolar) circuits in configurations analogous to CMOS. In this paper, the performance versus power dissipation of CBipolar circuits is examined using analytic equations. It is shown that for CBipolar to be superior to CMOS in both performance and power dissipation, narrow-gap-base heterojunction structures, such as Si emitter with Ge base or Si emitter with SiGe base, are required.

In an integrated circuit, transistors are used in standard configurations which occur repeatedly. In order to facilitate circuit analysis and synthesis for students, the concept of ‘transistor role’ has been introduced and a fundamental set of bipolar and MOS transistor roles was defined. This paper presents the LTspice implementation of the Bipolar and MOS Transistor Roles Building Block (BB) Library, with the most common transistor roles. Utilizing this BB Library, we then demonstrate the LTspice implementation of three representative analog integrated circuits: the LM741 Op Amp, the Open Loop CMOS Comparator MC14575 and a composite cascode high gain CMOS Op Amp. Simulation results prove that the transistor roles BB library works as expected, while facilitating circuit analysis, thus, allowing students to synthesize and simulate complex analog circuits more easily.

In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits.

A design approach to achieve low-voltage micropower class AB CMOS cascode current mirrors is presented. Both class AB operation and dynamic cascode biasing are based on the use of Quasi-Floating Gate transistors. They allow high linearity for large signal currents and accurately set quiescent currents without requiring extra power consumption or supply voltage requirements. Measurement results show that dynamic cascode biasing allows a wider input range and a linearity improvement of more than 23 dB with respect to the use of conventional biasing. A THD value better than −35 dB is measured for input amplitudes up to 100 times the bias currents. Two class AB current mirror topologies are proposed, with slightly different ways to achieve class AB operation and dynamic biasing. The proposed current mirrors, fabricated in a 0.5 µm CMOS technology, are able to operate with a supply voltage of 1.2 V and a quiescent power consumption of only 36 µW, using a silicon area 2 .

CMOS circuit design is based on two fundamental pillars: Understanding how MOS transistors operate, so a designer can innovate new circuit topologies and functions or know how to adjust the geometry and bias of transistors in existing circuits to meet performance goals; and understanding how accurate the MOS transistor models used in circuit simulators are, to know where the results of the detailed simulations used to verify circuit performance can or cannot be trusted.

Practical aspects of design of converters based on compound bipolar transistors are analyzed. The passage of a small reactive current through a compound bipolar transistor is analyzed using the example of a voltage inverter. A frequency converter with input protection is designed and loaded with an asynchronous motor at the output.

This paper presents bandgap reference (BGR) and sub-BGR circuits for nanowatt LSIs. The circuits consist of a nano-ampere current reference circuit, a bipolar transistor, and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed circuits avoid the use of resistors and contain only MOSFETs and one bipolar transistor. Because the sub-BGR circuit divides the output voltage of the bipolar transistor without resistors, it can operate at a sub-1-V supply. The experimental results obtained in the 0.18-μm CMOS process demonstrated that the BGR circuit could generate a reference voltage of 1.09 V and the sub-BGR circuit could generate one of 0.548 V. The power dissipations of the BGR and sub-BGR circuits corresponded to 100 and 52.5 nW.

Design of analog integrated circuits is discussed in this paper. The emphasis is on the biasing design of ICs using Fixator-norator pairs. Fixators are used to keep the driver transistors biased at the desirable operating points while the pairing norators are used to allocate and specify the bias-supporting components. A bias-supporting component is shown to be one of the two categories: 1) a DC voltage source or a DC current source/sink or 2) a power-conducting component. A power-conducting component is typically a resistor in lumped circuits but an active load or current mirror in an analog IC. Three types of active loads are introduced and their design is also discussed in this paper. Two examples, one in bipolar and one in CMOS technology, demonstrate the analog IC design procedure.

The design of an ultra-low voltage CMOS wideband LNA topology operating under a 0.6 V power supply with high gain and high IP2 is presented in this paper. The circuit performance is targeted towards use in direct conversion receivers, where a high IP2 is required. The LNA operates in sub-1 GHz applications reaching frequencies as low as 50 MHz, as it is required by IEEE 802.22 standard. The topology proposed here is based on the resistive-feedback inverter with a cascaded auxiliary amplifier to implement noise canceling. This cascaded amplifier is composed by a common-source (CS) amplifier and a very linear buffer at the output of the cascade. The high IP2 is obtained by a proper transistor biasing and by combining diodes with the load of the amplifiers with the highest non-linearity. This topology also works as a balun to comply with single-ended input from antennas and differential mixers as output loads. The post-layout simulations included bondwire inductances and pad capacitances parasitics. The results show a bandwidth of 50 MHz–1 GHz, voltage gain > 18 dB, NF < 3.8 dB, Sn < −13 dB and maximum IP2 of 38 dBm. The LNA power consumption is just 6.7 mW, excluding pad buffers.

Metal-oxide-semiconductor field effect transistor (MOSFET) intrinsic gain degradation caused by channel length modulation (CLM) effect is examined. A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4 (BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced, which only needs a few technology parameters. With this transistor intrinsic gain model, complementary metal-oxide-semiconductor (CMOS) operational amplifier (op amp) DC gain could be predicted. A two-stage folded cascode op amp is used as an example in this work. Non-minimum length device is used to improve the op amp DC gain. An improvement of 20 dB is proved when using doubled channel length design. Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain. After these, a full op amp DC gain scaling roadmap is proposed, from 130 nm technology node to 32 nm technology node. Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB. Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology. The prediction based on our simplified gain model agrees with SPICE simulation results.

This paper proposed a new high-order curvature compensation technique for a new bandgap voltage reference structure using the temperature characteristics of current gain β and emitter bandgap narrowing factor ΔE G of a lateral NPN bipolar transistor. The new structure can produce two voltage references, which are 1.209 and 2.418 V, respectively. The simulation results show that the temperature coefficients of the two output voltage are 0.52 ppm/°C, the PSRR is more than 60 dB for frequencies at 10 kHz, and the circuit dissipates 0.18 mW with 5-V supply.

This work rediscovers the attractiveness of feedback biasing when applied to circuits designed in nanoscale CMOS technologies. It is shown that very compact amplifiers can be obtained by utilizing a type of biasing that imposes minimal area overhead. We discuss how the undesired features of the nanoscale CMOS technologies actually help in the revival of this simple biasing method in newer technology generations. The measurement results of prototyped common-source (CS) amplifiers utilizing feedback biasing for application in medical ultrasound imaging systems are presented in this brief. The proposed feedback biasing is also suitable for amplifying signals from high-impedance sources that pose challenges on maintaining high input impedance for the voltage amplifiers while maintaining a very low input capacitance value. Measurements show that the proposed amplifier achieves a voltage gain of 28 dB, an output noise power spectral density of 0.11 (muV)2 Hz at center-frequency, and a total harmonic distortion of -30 dB, with the full-scale output at 30 MHz, while drawing 120 muA from a 1-V power supply. The amplifiers were fabricated in 90-nm CMOS technology and measured to be just 20 mum times10 mum.

This paper will introduce a new isolated version of the compensated base drive for high-power bipolar transistor switches. A unique pulse transformer is used to drive a high-power bipolar transistor by means of a compensated Darlington pair. This Darlington pair consists of an insulated gate bipolar driving transistor (IGBT) and a high-current single bipolar transistor. In high-efficient, high-power bridge applications of high-current switches, the saturation voltage should be ultra-low, which implies a high-power bipolar transistor in deep saturation. This isolated base-drive circuit is described and evaluated in these applications.

In this chapter, the transistors have been grouped into two major categories viz. Bipolar junction transistors (BJTs) and Field effect transistors (FETs). They have been further classified into p-n-p and n-p-n types; MESFET, MISFET, MODFET, MOSFET, n-channel, p-channel types etc. The details of BJTs such as their construction, fundamentals of operation, meaning and symbols of n-p-n and p-n-p are given. Forward and reverse biasing, transistor currents, circuit configurations and their characteristics are described. Comparison between CB, CE and CC configurations is presented. Amplification with different configurations of BJTs, their characteristics and uses, and phase reversal are discussed. Specifications of transistors and their terminal identifications are given. Meanings of cascade amplifier, Debye screening length, and Kirk effect are explained. Minute insight into the various topics are given through solved numerical and theoretical examples. Review questions, numerical problems and objective type questions are also given with their answers.

Current status is presented for the development and experimental verifcation of 0.18 μm high voltage CMOS integrated circuits with pad-based ESD protection made with the use of lateral bipolar transistor. Developed I/O pads provide 2000 V ESD protection.

A metal–oxide–semiconductor field-effect transistor (MOSFET) (or insulated-gate bipolar transistor (IGBT)) is controlled by the application of a voltage between its gate and its source (or emitter): for voltages between zero and a few volts, the transistor is turned off, then once a threshold voltage ( V GSth or V GEth ) is reached, the transistor allows current to pass, at first in a linear mode, and then tending toward a state of saturation. To ensure this happens, a voltage significantly higher than V GSth (or V GEth ) must be applied in order to guarantee the saturation: in practice, a voltage between 10 and 15 V is sufficient for this purpose. As the gate is physically equivalent to a capacitor frame, the transistor behaves in the same way from a control perspective.

In this paper, the performance of high-voltage (10kV) 4H-SiC n- and p-channel IGBTs and n-channel MOS-Gated Bipolar Transistor (MGT) are investigated and compared using 2- dimensional numerical simulations. We have found that the MGT in SiC is not suitable for applications at high blocking voltages and the p-channel IGBT is a better choice because of a much higher conductivity modulation in the drift region.

Like many bumps on the electrotechnological landscape, the Gummel-Poon bipolar transistor model has remained in existence for both historical and technical reasons. An extended version of the model was incorporated into SPICE, which eventually became the dominant software tool for electronic circuit design. The Gummel-Poon base-resistence model began as an attempt to make a physically correct description of base resistance yet created more problems than it solved.

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino (SD) logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a SD circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a SD circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a SD circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced.

This paper shows a systematic approach to calculate and to minimize mechanical-stress-related problems in bandgap voltage references. Mechanical stress is the main cause of long-term drift and packaging-induced inaccuracy in bandgap voltage references. Especially, low-cost epoxy packaging can cause a large mechanical stress, being in the range from -200 to +200 MPa. This stress shows local variations over the chip area and changes over time or during thermal cycling. Due to the piezojunction effect, this stress causes changes and drift in the base-emitter voltages of bipolar transistors and consequently in the output voltage of bandgap references. In this paper, it is shown that, even when using low-cost IC and packaging technology, a bandgap reference with a high immunity for the effects of mechanical stress can be realized.

Two new class AB output stages for CMOS op-amps are proposed with accurate quiescent current control. The second proposed stage also provides accurate control of the minimum current through the output transistors. The proposed stages can be operated with a supply voltage close to a transistor threshold voltage. A dynamic biasing scheme allows them to operate in a wide range of supply voltages. Using these stages two opamps have been designed using a 0.8 μm CMOS technology. Experimental results show a unity gain frequency of 15 MHz with 290 μA of quiescent current and a 10 pF load, using a 1.5 V single voltage supply.

A quadrature voltage controlled oscillator (QVCO) with −111 dBc/Hz average phase noise at 1MHz offset across an output frequency range of 48.9–50.3 GHz is presented. The design employs a modification of the Armstrong technique of using a transformer in the LC tank to improve the phase noise by reducing the single-ended component of the tank capacitance in a differential cross-coupled design and by separating the gate and drain transistor bias. Tuning is achieved by an accumulation MOS varactor and a thermometer-coded bank of 14 switched capacitors. The design consumes 23 mA from a 1.3 V supply and occupies an area of 0.25 mm2 in 90 nm CMOS technology.

A simple log-domain integrator that operates nominally with a supply voltage of 1.2 V is proposed. It does not employ p-n-p or positive metal-oxide-semiconductor (PMOS) transistors in the signal path. This has two advantages: (1) It makes the integrator suitable for high-frequency applications. (2) The circuit can be implemented using low-cost bipolar processes rather than the more expensive bipolar complementary metal-oxide-semiconductor (BiCMOS) processes or the bipolar processes featuring high-quality p-n-p transistors. A third-order Chebyshev prototype filter, employing the proposed integrator, is realized using a semicustom bipolar array. It consumes 282 /spl mu/A per pole for a cutoff frequency of 1.5 MHz, achieving a 40.5 dB dynamic range. For lower biasing currents, the circuit can operate from a supply voltage as low as 0.9 V. Detailed experimental results are reported and discussed.

The conventional DC Ebers-Moll model of the bipolar transistor with three different types of piecewise-linear characteristics of the emitter and collector diodes is analysed. Separate necessary and sufficient conditions in the form of inequalities relating the current gains and the characteristics or weakly no-gain are derived. They are of practical importance in various theoretical and computational studies of diode-transistor circuits.

The new architecture of the differential stages (DS), that provides the increase of the voltage gain on 1 or 2 orders without using of the classical active loads (current mirrors) on p-n-p transistors is considered. The recommended application field is analog and analog-to-digital circuits with the low supply voltage. The effect of increasing of the gain of DS at relatively low-ohmic resistors of the collector load (R1=R2=600÷800 Ohms) is provided due to the introduction of a special scheme of their cancellation. The increase of the gain up to 40÷70 dB requires the mismatch of the rating values of the resistors R1, R2 in the range of 5÷10%. The results of the computer simulation of DS for the bipolar technological process HJV Zarlink Semiconductor are shown.

This paper presents the design of voltage and current references in short channel CMOS technologies operating with Low Supply Voltages (< 1.2V). The objective is to design simple circuits having good Power Supply Rejection (PSR) with minimal power consumption and area which are easy to re-use. The references are based on class AB CMOS inverters and current mirrors. A voltage reference is obtained as a scaled sum of two diode voltages carrying different current densities so that it is equal to a fraction of the bandgap voltage of silicon. The current reference is obtained by calibrating a simple current source using the bandgap voltage and a switched capacitor conductance clocked by the system clock.

We demonstrate in this paper that it is possible to operate a certain bipolar transistor as an amplifier using only the emitter and base without using the collector. This study was performed based on the novel hypothesis that the bipolar transistor works by the internal photovoltaic effect.

Design of a sub-1V supply, half bandgap voltage reference (Vr) is proposed, which can generate Vr of about 620mV and operate with power supply voltage (VDD) as low as about 750mV at 0°C. To enhance manufacturability and facilitate ease of design portability across different process nodes, the design is implemented in standard 180nm digital CMOS without the need for any special CMOS processes or non-conventional devices. The proposed topology only utilizes parasitic substrate bipolar junction transistors (BJT), poly resistors, and normally configured CMOS transistors that chiefly operate in subthreshold. Lower VDD is achieved by segregating BJTs from the resistors used in the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) signal loops. Such configuration results in lowering the emitter-base voltage (VEB) via biasing the BJTs at n-times (i.e. 100s of times) lower currents than the PTAT and CTAT resistors and signal loops. Therefore, the scarce VDD headroom in sub-1V applications is freed-up in the PTAT loop from VEB by VT × ln (n), or in the range of typically 10%-15% of VDD. Moreover, biasing the BJT loop at nano-ampere currents keeps the power consumption low, while it avoids using prohibitively large PTAT or CTAT resistors.

The onset of impact-ionization-induced instabilities limits the operating range of Si-bipolar transistors, especially in power stages. Therefore, analytical relations which characterize the onset of instabilities are derived for different driving conditions (mainly V/sub BE/=const. and I/sub E/=const.) and arbitrary transistor geometries. They allow the designer and technologist to calculate the maximum usable dc output voltage in dependence on transistor dimensions and technological parameters. As a consequence, the voltage range above BV/sub CE0/ can now be more intensively and reliably used and thus the performance potential of a given technology can be better exploited. However, the reduction of the maximum tolerable output voltage with increasing emitter (or collector) current must be carefully considered. The presented theory and analytical results are verified by three-dimensional (3-D) transistor simulations and by measurements.

Small-signal bipolar junction transistor (BJT) amplifiers, including common-emitter (C-E), common-base, and common-collector amplifiers, are the basic building blocks of many analog integrated circuits. An experimental investigation of the physical analysis of the frequency response and related parameters of these amplifiers have been performed in some details. The analysis uncovers fundamental reasons underlying the frequency response of the amplifiers. It indicates that although both the load resistance R L and the collector resistance R C , influence the voltage gain, for example, of a C-E amplifier, none of them should be very high to yield the highest value of the voltage gain. The distortion of the wave form of the output signal is found to be a serious problem in BJT amplifier circuits. This problem is particularly very serious in C-E amplifier with square wave signal and at high frequencies. Although by-pass capacitor plays a crucial role in minimizing this problem, the contribution of the coupling capacitors in this regard cannot be ruled out. Physical reasons of the distortion has been discussed in some details.

This study presents an ultra-low-power 24 GHz low-noise amplifier (LNA) using 0.13 μm CMOS technology. We propose of using the minimum noise measure (MMIN) as the guideline to determine the optimal bias and geometry of the transistors in the circuit. The power-constrained simultaneous noise and input matching (PCSNIM) technique is also employed for this design. With the proposed design approach, the LNA achieves a peak gain of 9.2 dB and a minimum NF of 3.7 dB under a supply voltage of 1 V. The associated power consumption is only 2.78 mW.

In this paper, a novel lateral bipolar transistor on thin film silicon-on-insulator (SOI) is presented. With a small emitter size of 0.12/spl times/3.0 /spl mu/m/sup 2/, low base resistance of 270 /spl Omega/ due to a novel Co silicided base electrode and low base-collector parasitic capacitances of 1.4 fF due to SOI material, it achieves the highest f/sub max/ of 67 GHz among SOI bipolar transistors. Also, the low emitter-base capacitance of 1.5 fF and the low collector-substrate capacitance of 2.5 fF are realized. The transistor has a simple structure, which is fabricated with simplified processes without any new sophisticated technologies, excluding trench isolation and epitaxial base used in current bipolar transistors. This can lower the fabrication cost of transistors. We have demonstrated the possibility of lateral bipolar transistor on thin film SOI as next-generation device for RF analog applications.

A transistor circuit consisting of linear positive resistors, q exponential diodes, and p Ebers-Moll modeled bipolar transistors has at most (d+1)/sup d/2/sup d(d-1)/2/ isolated DC operating points where d=q+2p. If, instead of bipolar transistors, the circuit employs Shichman-Hodges modeled field-effect transistors, then it can have at most 2/sup p/ 3/sup 2p/(4p+q+1)/sup q/2/sup q(q-1)/2/ isolated DC operating points. Bounds are also obtained for the number of DC operating points in circuits using other transistor models.

This paper introduces two original equations for biasing the common-emitter bipolar-junction transistor (BJT-CE) amplifier. These equations permit placing both Q-point coordinates (i.e. current and voltage) within known bounds in the presence of transistor parameter variations. An illustrative design example is provided.

Record-high drive current on the order of 3-5mA/μm is demonstrated in lateral silicon bipolar transistors on SOI. This is achieved by scaling quasi-neutral base width to below 10nm. The heavily doped collector enables the transistor to operate in high level injection regime without the detrimental base push-out effect. Measured cut-off frequency is the highest for a lateral bipolar and has a broad peak, confirming its immunity to base push-out. Functional complementary bipolar ring oscillator operating in the full saturation region is reported for the first time. The salient features of CMOS-compatible process and design, high current drive capability and low voltage bipolar logic present exciting opportunities for lateral SOI bipolar to complement CMOS.

A low-temperature coefficient, curvature-compensated CMOS bandgap voltage reference (BGR) is presented in this paper. The design was implemented in standard 0.18μm CMOS process with 1.8V power supply. The compensation is achieved generating the negative temperature coefficient (TC) voltage with a quadratic temperature dependent current biasing a bipolar transistor. In addition, the design has a 4-bit trimming circuit to compensate for process variations. The output voltage is 1.225V and shows a TC lower than 2ppm/°C over a temperature range of 160°C (-20°C to 140°C). The bandgap reference consumes 620μW and its total layout area is 217×147μm2.

As the transistor dimension keeps shrinking following trend predicted by Moore's Law, the voltage that transistor can sustain reliably is also reducing. For certain serial interface protocols (like the ubiquitous Universal Serial Bus (USB)) and some legacy input/output interfaces, high voltages like 1.8V, 3.3V and even 5.0V are still being used for protocol compliance. It is costly in silicon fabrication to provide transistors with different gate-oxide thickness to cater for various high voltage and speed requirements. In order to minimize the type of gate oxide thickness in advanced silicon process, circuit innovation is usually required to enable transistor to operate with voltage higher than its reliability limit, yet protected from electrical overstress (EOS). This paper discusses a new circuit architecture that is able to detect voltage source as well as to switch between external source and internal biasing voltage to ensure all transistors operating with high voltage are not exposed to the voltage limit. This circuit is low power in nature since it does not consume static current. By having this protection scheme, this would enable the use of transistor to support high-voltage application without incurring cost of having additional thicker gate-oxide transistor. In terms of application, this architecture can be used in integrated chip design involving various high-voltage supplies.

A low voltage bandgap architecture is proposed. The opamp in the proposed bandgap is used for both generating the output reference voltage (Vref) and achieving low output impedance. To allow Vref to have different values within the supply voltage limits, a transconductor is proposed and used in conjunction with the opamp to supply the biasing currents of the bipolar transistors. A 1V, ~33.5μW bandgap design example based on a 0.18μm CMOS process is presented. For a load current between 0mA and 50mA with a temperature range in between -20°C and 100°C, the variations on the nominal Vref (632.94mV) was within -0.38% and +0.11% with a load regulation of

In spectroscopy systems where the front-end amplifier is an external circuit, charge sensitive preamplifiers have been shown to be superior in performance with respect to voltage amplifiers as the first stage of amplification. The paper studies how these two circuit configurations behave when they are integrated in high resolution semiconductor detectors of very small capacitance. This paper for the first time compares, in this new condition, the stability of amplification of the source follower with the optimum behavior of the charge preamplifier, reporting its dependence on the detector bias, on the input transistor bias, and on the operating temperature. This paper then discusses the consequent loss in linearity and resolution that a system with an integrated source follower may undergo depending on the type of reset mechanism. The point of how the instabilities of the integrated feedback capacitance limit the performance of an integrated charge amplifier is also addressed. The analysis is based on experimental results obtained with the same detector with integrated electronics used in the two different configurations.