1. Design Requirements for Steeply Switching Logic Devices
- Author
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Tiehui Liu, Hei Kam, and Elad Alon
- Subjects
Engineering ,business.industry ,Electrical engineering ,Integrated circuit design ,Dissipation ,Electronic, Optical and Magnetic Materials ,Logic synthesis ,CMOS ,Logic gate ,Low-power electronics ,MOSFET ,Electronic engineering ,Electrical and Electronic Engineering ,business ,Efficient energy use - Abstract
Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy-performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal Ion/Ioff and Edyn/Eleak ratios are set only by circuit-level parameters as well as the device transfer characteristic off-state Soff, on -state Son, and effective Seff inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal Edyn/Eleak ratio is approximately (K/2)(Seff/Soff) - 0.56(Son/Soff) - 0.56, where K ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for Soff, Son, and Seff are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope S is insufficient, since energy dissipation is set mainly by Seff and not by S. Finally, the general shape of the energy-delay curve is also set by these inverse slopes, with its steepness directly proportional to Son/Soff. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology.
- Published
- 2012