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High switching current density has been a key bottleneck for phase change memory (PCM) technology. Here, we demonstrate interfacial thermoelectric heating (TEH) as a promising way of tackling this challenge. We use TEH induced by a thin Bi2Te3 interfacial layer to demonstrate $\sim 2\times $ reduction of reset current density (${J} _{\text{reset}}$) and power (${P} _{\text{reset}}$) compared to control PCM devices based on Ge2Sb2Te5 (GST). Measurements of polarity-dependent reset current and power in well-cycled devices reveal the strong TEH caused by the Bi2Te3 interfacial layer. The TEH origin of ${J} _{\text{reset}}$ reduction is further confirmed by electro-thermal simulations. Such TEH-engineered PCM devices are scalable with the bottom electrode diameter and thus could be promising for high density data storage applications. [ABSTRACT FROM AUTHOR]

A physics-based compact model for retention behaviors of conductive-bridge random access memory (CBRAM) is developed by modeling: 1) the material-dependent metal atom transport from the conductive filament into the electrolyte; and 2) the conduction percolation controlled by the atom concentration. Considering the material properties of the metal and electrolyte, this compact model can well reproduce the retention behaviors of the CBRAM in both low resistance state and high resistance state (HRS) for various material stacks under various operating temperatures. Two types of HRS resistance shift can be reproduced by accurately modeling the percolation paths. The compact model can enable the reliability projection of cells in a crossbar array. [ABSTRACT FROM AUTHOR]

Control of cation injection into the switching layer of conductive-bridge random access memory (CBRAM) during switching is a critical factor for CBRAM reliability. Although extrinsic approaches such as the insertion of a transistor in series have proven effective, solutions intrinsic to the CBRAM itself, which are desired for high density cross-point or 3-D vertical memory arrays, are quite limited. In this letter, we show the significant improvement of cycling endurance for Cu-based CBRAM by scaling the switching layer area down to 30 nm in diameter. Further study suggests that the injection of excessive Cu ions into the switching layer is suppressed owing to spatial limitation during the formation of the conductive filament. These results indicate that the area scaling of the switching layer is an effective solution for achieving highly reliable CBRAM devices. [ABSTRACT FROM PUBLISHER]

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1–7 pJ per bit and has a high programming endurance of up to 10^6\vphantom \sum ^R^R cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of <1~\mu \textA are achieved. [ABSTRACT FROM PUBLISHER]

This paper describes the improvement of pull-in stability, contact properties, and reliability of laterally actuated nanoelectromechanical relays by partitioning the mechanical and electrostatic domains in the relay structure. Separation of the two physics allows us to individually optimize the structural stiffness and the actuation voltage to increase the contact pressure and reduce the ON-state resistance without applying excessive drain voltage. The devices can tolerate more than 200% overdrive gate voltage, resulting in near 100% increase in contact force, and reducing the contact resistance from $\sim 10$ G $\Omega $ to $\sim 23$ K $\Omega $ . For a given overall device dimension, tailoring the mechanical and electrostatic elements independently also enables us to control the pull-in and pull-out voltages, which have different design requirements for different applications. The measurement results show that the pull-in/pull-out hysteresis could vary between 30% and 60% of the actuation (pull-in) voltage. Increasing the mechanical force without affecting the device actuation voltage improves the relay reliability by reducing the possibility of failure due to source–drain stiction when the relay is switched ON. As a proof of concept, mechanical relays are fabricated using polycrystalline silicon coated by a titanium nitride layer deposited via plasma enhanced atomic layer deposition. [2014-0018] [ABSTRACT FROM AUTHOR]

The vertical scaling for the multi-layer stacked 3D vertical resistive random access memory (RRAM) cross-point array is investigated. The thickness of the multi-layer stack for a 3D RRAM is a key factor for determining the storage density. A vertical RRAM cell with plane electrode thickness (tm) scaled down to 5 nm, aiming to minimize 3D stack height, is experimentally demonstrated. An improvement factor of 5 in device density can be achieved as compared to a previous demonstration using a 22 nm thick plane electrode. It is projected that 37 layers can be stacked for a lithographic half-pitch (F) = 26 nm and total thickness of one stack (T) = 21 nm, delivering a bit density of 72.8 nm2/cell. [ABSTRACT FROM AUTHOR]

In this paper, recent progress of binary metal–oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal–oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed. [ABSTRACT FROM PUBLISHER]

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 \mu\A and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology. [ABSTRACT FROM AUTHOR]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number (\sim1000) of cyclic SET–RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) are promising candidates for transistors and interconnects for nanoelectronic circuits. Although CNTs intrinsically have excellent electrical conductivity, the large contact resistance at the interface between CNT and metal hinders its practical application. Here, we show that electrical contact to the CNT is substantially improved using a graphitic interfacial layer catalyzed by a Ni layer. The p-type semiconducting CNT with graphitic contact exhibits high on-state conductance at room temperature and a steep subthreshold swing in a back-gate configuration. We also show contact improvement to the semiconducting CNTs with different capping metals. To study the role of the graphitic interfacial layer in the contact stack, the capping metal and Ni catalyst were selectively removed and replaced with new metal pads deposited by evaporation and without further annealing. Good electrical contact to the semiconducting CNTs was still preserved after the new metal replacement, indicating that the contact improvement is attributed to the presence of the graphitic interfacial layer. [ABSTRACT FROM PUBLISHER]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

This paper introduces a novel structure for filamentary-conduction-type resistance change memory. The new structure utilizes the fringing field from the top metal electrode to effectively confine the position of the filaments in the cell. Nanoscale (100–50 nm) memory cells are fabricated using nickel oxide (NiO) thin film as the resistance-switching layer to demonstrate the feasibility and functionality of the new structure. The fabricated nanoscale memory cells achieved low reset current (100–200 \mu\A), narrower distribution in low-resistance states, and higher on/off ratio than those of the standard structure. In addition, good scalability down to 50 nm was demonstrated. [ABSTRACT FROM AUTHOR]

A physics-based compact device model is developed for the conducting-bridge random-access memory (CBRAM). By considering the dependence of ion migration velocity on the electric field, the vertical and lateral growth/dissolution dynamics for the metallic filament are investigated. Both time-dependent transient and “quasi-static” switching characteristics of the CBRAM are captured. Moreover, the I–V characteristics of the CBRAM can be reproduced. By further considering the compliance effect on the size of the metallic filament, the on-state resistance modulation is fitted, and the multilevel capability is included in the model. This model is verified by the experiments data from the \Ag/Ge0.3\Se0.7-based CBRAM cells. This model reveals that experimentally measured switching parameters such as the threshold voltage and the cell resistance are dynamic quantities that depend on the programming duration time. The time-dependent switching process of the CBRAM is quantified, thus paving the way for a compact SPICE model for circuit simulation. [ABSTRACT FROM PUBLISHER]

This letter presents the novel CMOS-compatible all-metal-nitride resistive random access memory (RRAM) devices based on the TiN/AlN/TiN stack. The device has low operation current <100 \mu A, retention of > 3\times 10^{5} s at 150 °C, and ac endurance of up to 10^{5}$ Hz. The device switch characteristics are found to agree with the filamentary switch mechanism. In addition, the RRAM devices built with an additional hafnium nitride capping layer have showed less switch voltage variations and stable switch characteristics. [ABSTRACT FROM PUBLISHER]

In this letter, we examine the role of the Ti capping layer in HfOx-based resistive random access memory (RRAM) devices on the memory performance. It is found that with a thicker Ti capping layer, the fresh device initial leakage current increases and as a result, the forming voltage decreases. In addition, with a thin Ti layer of <3 nm (on top of 8-nm HfOx), there is no resistive switching, while by inserting a thicker Ti layer of 10 nm, the memory window enlarges to about two orders. Very good uniformity has also been observed in thick Ti capping devices, demonstrating the effectiveness in RRAM device engineering. It is believed that the Ti layer serves as an oxygen reservoir, by extracting oxygen during device formation and electrical forming process and facilitates resistive switching thereafter. [ABSTRACT FROM AUTHOR]

HfOx-based resistive random access memory with an active area down to few nanometers (<10~nm) in diameter is fabricated and characterized. Scaling trends for forming and switching characteristics are presented. For the smallest device with an active area of few nanometers in diameter, ac switching endurance of 10^8 cycles with more than 100\,\times resistance window is demonstrated. In addition, multiple resistance states are shown to be stable after 10^5 read cycles and 10^5~s baking at 150^\circC. [ABSTRACT FROM PUBLISHER]

The reset mechanism of metal oxide RRAM has been attributed to oxygen ion migration assisted by Joule heating. Here, we present a phenomenological model to provide a unified explanation for both the unipolar and bipolar resistive switching mechanisms. Numerical simulation results reveal that the switching mode is determined by the electrode/oxide interface property. Without/with an interfacial barrier, unipolar/bipolar switching behavior is obtained. This model combines the previous thermal dissolution model and ion migration model and thus can explain many experimental observations such as the electrode-material-dependent switching polarity and the voltage–time dilemma between fast switching and long retention. [ABSTRACT FROM AUTHOR]

\Al2\O3-based RRAM devices were fabricated using atomic layer deposition under 100 ^\circ\C and 300 ^\circ\C deposition temperatures, respectively, and their resistance-switching behaviors were investigated. Both devices show unipolar switching if the top electrode (TE) is made of Ti/Al, whereas the bipolar phenomenon is observed when TE is pure aluminum. Devices fabricated at higher temperature give better uniformity and higher resistance ratio. Ultralow RESET current (\sim\!\!\1\ \mu\A) was obtained, together with adequate voltage margin. [ABSTRACT FROM AUTHOR]

In this paper, we employed Ramen spectroscopy to monitoroxygenmovement at the electrode/oxide interface by inserting single-layergraphene (SLG). Raman area mapping and single-point measurements shownoticeable changes in the D-band, G-band, and 2D-band signals of theSLG during consecutive electrical programming repeated for nine cycles.In addition, the inserted SLG enables the reduction of RESET currentby 22 times and programming power consumption by 47 times. Collectively,our results show that monitoring the oxygen movement by Raman spectroscopyfor a resistive random access memory (RRAM) is made possible by insertinga single-layer graphene at electrode/oxide interface. This may openup an important analysis tool for investigation of switching mechanismof RRAM. [ABSTRACT FROM AUTHOR]