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To satisfy the ever-increasing requirement from load side and improve the power quality through harmonic content reduction, the paralleled converters’ structure is seen to be an interesting solution. However, paralleled converters, in which the same dc and ac sides are shared, suffer from a major challenge related to the excessive circulating currents due to the difference in the induced common-mode voltage (CMV) in each converter. This voltage difference is due to the instantaneous potential difference between paralleled phase-legs, due to the discrepancy in circuit and control parameters of paralleled converters. Consequently, zero-sequence circulating current (ZSCC) as well as differential-mode circulating current (DMCC) shall appear between the paralleled converters. In this context, this article utilizes the interleaved pulsewidth modulation (PWM) concept for the ZSCC and DMCC reduction in paralleled split-source inverters (SSIs), where this SSI is a single-stage dc–ac converter and the prior mentioned operation and associated issues have not been investigated yet. This article describes the three-phase SSI structure and its basic operation, and shows the corresponding CMV waveform. Then, based on the shown analysis, an interleaved discontinuous PWM strategy is proposed to restrain the CMV amplitude and reduce the induced circulating currents. Furthermore, the effect of changing the modulation index and interleaving angle on the overall converter behavior has also been evaluated in case of using SSI. The analysis and simulations revealed the effectiveness of the proposed modulation strategy compared to counterparts. Finally, the shown simulation results are validated with an experimental prototype of 1 kW. [ABSTRACT FROM AUTHOR]

This paper proposes a family of spread-spectrum schemes, several of which are new, for conducted-noise reduction in dc–dc converters. The schemes use three randomized parameters to generate the switching signals: carrier frequency, duty ratio, and pulse position. The increasing performance and cost reduction of field-programmable gate array (FPGA) technology have made the application of these schemes possible in this field. A theoretical framework for a general representative scheme is provided. Then, the proposed schemes are designed and implemented using an FPGA-based controller. Furthermore, the effect of using the proposed controller on common-mode, differential-mode, and total conducted-noise characteristics of the dc–dc converter is experimentally investigated. In addition, the three randomization parameters are swept to determine the values that best achieve the conducted-noise spectrum spread. All studied cases are designed, implemented, and experimentally investigated. Then, the conducted-noise spectra are compared. The experimental results show that the use of the proposed controller with the determined randomization values significantly improves the conducted-noise spectrum and effectively reduces the noise peaks at both high- and low-frequency ranges. [ABSTRACT FROM AUTHOR]

As an effective means of suppressing electromagnetic interference (EMI) noise, the impedance balancing technique has been adopted in the literature. By suppressing the noise source, this technique can theoretically reduce the noise to zero. Nevertheless, its effect is limited in practice and also suffers from noise spikes. Therefore, this paper introduces an accurate frequency modeling method to investigate the attenuation degree of noise source and redesign the impedance selection accordingly in order to improve the noise reduction capability. Based on a conventional boost converter, the common mode (CM) noise model was built by identifying the noise source and propagation paths at first. Then the noise source model was extracted through capturing the switching voltage waveform in time domain and then calculating its Fourier series in frequency domain. After that, the conventional boost converter was modified with the known impedance balancing techniques. This balanced circuit was analyzed with the introduced modeling method, and the equivalent noise source was precisely estimated by combining the noise spectra and impedance information. Furthermore, two optimized schemes with redesigned impedances were proposed to deal with the resonance problem. A hardware circuit was designed and built to experimentally validate the proposed concepts. The experimental results demonstrate the feasibility and effectiveness of the proposed schemes. [ABSTRACT FROM AUTHOR]