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A new Pd|HfO2|AlGaN|GaN metal-oxide-semiconductor (MOS) enhancement-mode high electron mobility transistor (HEMT) is fabricated with low-temperature sensitization, activation, electroless-plating, and two-step gate-recess approaches. Experimentally, a high positive threshold voltage Vth of 1.96 V, a very low gate leakage IG of 6.3 × 10–8 mA/mm, a high maximum extrinsic transconductance gm, max of 75.3 mS/mm, a high maximum drain saturation current ID, max of 266.9 mA/mm, and a high ON/OFF current ratio of 7.6 × 107 are obtained at 300 K. Moreover, the related temperature-dependent characteristics, over temperature ranges from 300 to 500 K, are comprehensively studied. The very low temperature coefficients on gate current, drain saturation current, transconductance, and threshold voltage confirm the thermal-stable capability of the studied device. Therefore, based on these advantages, the studied Pd|HfO2|AlGaN|GaN MOS structure is suitable for the development of high-performance HEMTs.

Unlike the conventional GaAs- and InP-based enhancement/depletion-mode (E/D-mode) transistors, the improved gate characteristics of the AlGaAs/InGaAs E-mode high electron mobility transistors (HEMTs) by way of hybrid gate recesses to remove the n-AlAs/i-GaAs/n-AlGaAs virtual channel layers upon 2DEG channels are demonstrated. As compared to the D-mode device (sample A), the gate reverse currents are effectively reduced by 45 and 102 times for the E-mode devices with additional gate recess time of 24 s (sample B) and 30 s (sample C) to remove part of the virtual channel layers, respectively. Under gate forward bias, the hybrid gate recesses also enable the gate turn-on voltages to increase. Furthermore, the threshold voltages of –1.25, 0.09, and 0.22 V are observed in the samples A, B, and C, respectively. The maximum transconductances of 187.3, 209.2, and 243.4 mS/mm and saturation current density of 482.8, 410.6, and 347.4 mA/mm are obtained in the samples A, B, and C, respectively.

The characteristics of GaN-based light-emitting diodes (LEDs) with a hybrid structure incorporating a microhole array, 45 sidewalls, and an appropriate SiO2 nanoparticle (NP)/microsphere (MSs) passivation layer are studied and reported. The use of a SiO2 NP/MSs passivation layer causes a remarkable reduction in reverse-biased leakage current. The employment of this hybrid structure leads to substantial enhancements in optical properties without any degradation in electrical performance. In addition, a lower content of SiO2 NP in the mixed SiO2 NP/MSs solution leads to enhanced optical behavior due to the improved transmittance. Experimentally, as compared with a conventional LED (Device A), the studied Device E shows 50.6%, 50.9%, 48.4%, and 49.9% enhancements in light output power, luminous flux, luminous efficacy, and wall-plug efficiency, respectively. These advantages are mainly attributed to the increased scattering probability and the opportunity to find photon escape cones as well as the reduced total internal reflection and Fresnel reflection effects. Therefore, the studied hybrid structure provides a promise for high-performance GaN-based LED applications.

An interesting device design including a zirconium oxide (ZrO2) current blocking layer (CBL) and a ZrO2 surface passivation layer (SPL) is employed to manufacture a GaN/InGaN light-emitting diode (LED). Based on the inherently good performance of ZrO2, the current spreading effect and the undesired surface leakage are efficiently enhanced and suppressed, respectively. Energy-dispersive X-ray spectroscopy (EDS), atomic force microscopy (AFM), scanning electron microscopy (SEM), and transmission electron microscopy (TEM) are used to study the relevant properties. It is found that by series calibration, 50 nm is the proper thickness of the ZrO2 CBL and SPL. The peak emission wavelength of the proposed LEDs is around 452 nm. Experimentally, at the operating condition of 110 A cm−2, the proposed Device L3 with a 50 nm-thick ZrO2 CBL and a 50 nm-thick ZrO2 SPL demonstrates improvements of 66.1% in light output power (LOP) and 64.5% in wall plug efficiency (WPE) as compared to a traditional Device L1 without the specific design. Furthermore, the proposed Device L3 presents a notable enhancement in the light emission mapping image in comparison to the traditional LED. So, the proposed device design which incorporates a proper ZrO2 CBL and ZrO2 SPL, is beneficial for manufacturing GaN/InGaN LEDs.

An Al2O3 thin film is deposited on the interdigitated electrodes to fabricate a resistive hydrogen sensor. In addition, the Pd nanoparticles (NPs)/Pd film by vacuum thermal evaporation system on the Al2O3 film acts as catalytic metals for hydrogen detection. Due to the Pd NPs with an increased surface area to volume ratio as well as the spill-over effect, the catalytic activity could be improved to enhance the gas sensing performance. The experimental results showed that the sensing response ratio is 14.4% in 1000 ppm H2/air at 300 °C, which is suitable for high-temperature hydrogen detection. The studied Pd NPs/Pd/Al2O3 resistive sensor exhibits the advantages of in high-temperature operation, simple structure, easy fabrication process, and relatively low cost.

In this article, Al0.28Ga0.72N/AlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) with Ni/Au gate metal electrode are demonstrated. NiO or Al2O3 gate oxide layer is employed as a gate dielectric layer effectively decreases the gate leakage current, enhances drain current density, and transconductance, simultaneously. As compared with the metal-semiconductor (MS) Schottky-gate device, excellent characteristics are achieved for the MOS-HEMT with NiO (Al2O3) gate oxide layer, which include maximum drain-to-source saturation current density of 626.5 (692.0) mA/mm, maximum transconductance of 87.6 (94.2) mS/mm, gate-to-drain leakage current of 1.47  10-7 (8.21  10-11) mA/mm, threshold voltage of -3.48 (-3.45) V, gate voltage swing of 2.88 (3.08) V, respectively. Experimentally, the MOS-HEMT with an Al2O3 gate oxide layer shows good potential for signal amplification and circuit applications.

A new and simple Al/aluminum-doped zinc oxide (AZO) composite structure is proposed to act as a transparent conductive layer (TCL) for GaN-based LEDs. The Al/AZO composite layers effectively improve the current spreading performance, compared with an AZO TCL. Experimentally, the specific contact resistance of the studied Al/AZO LED is reduced by about 27.6%, compared with an AZO LED. In addition, under an operating current of 20 mA, the forward voltage and light output power (LOP) of the studied Al/AZO LED are decreased by 0.15 V and increased by 19.5%, respectively. Uniform and enhanced intensities are also found in light emission mapping images of the studied Al/AZO LED. Consequently, based on benefits including simple structure and improved electrical and optical properties, the studied Al/AZO TCL is suitable for GaN-based LED applications.

The Characteristics of GaN-based LEDs with hybrid microhole arrays and SiO2 microspheres (MSs)/ nanoparticles (NPs) are comprehensively studied. The SiO2 MSs/NPs antireflection coating, deposited by a rapid convection deposition, acts as a passivation layer of GaN-based LEDs. Since the critical angle could be enlarged by antireflection coating, Fresnel reflection could be reduced. In addition, due to the roughened surface of SiO2 MSs/NPs antireflection coating, the scattering effect could also be increased. Thus, the light extraction efficiency could be further enhanced. As compared with a conventional LED with a planar aluminum-doped zinc oxide current spreading layer (Device A), the studied device with the proposed hybrid structure and a sputtered SiO2 passivation layer (Device E) causes a suppressed leakage current and % enhancements on light output power, external quantum efficiency, and wall-plug efficiency performance.

Based on an electrophoretic deposition (EPD)-gate approach, a Pt/AlGaN/GaN heterostructure field-effect transistor (HFET) is fabricated and investigated at higher temperatures. The Pt/AlGaN interface with nearly oxide-free is verified by an Auger Electron Spectroscopy (AES) depth profile for the studied EPD-HFET. This result substantially enhances device performance at room temperature (300 K). Experimentally, the studied EPD-HFET exhibits a high turn-on voltage, a well suppression on gate leakage, a superior maximum drain saturation current, and an excellent extrinsic transconductance. Moreover, the microwave performance of an EPD-HFET is demonstrated at room temperature. Consequentially, this EPD-gate approach gives a promise for high-performance electronic applications.

A simple platinum nanoparticle (Pt NP)/WO3 semiconducting metal oxide (SMO)-based structure is fabricated and completely studied as a hydrogen gas sensor. In this work, simple rapid thermal evaporation (RTE) was employed to fabricate Pt NPs. This approach could easily produce Pt NPs with a small grain size and uniformity on the WO3 thin film. Experimentally, at 200 °C, the studied device exhibited an excellent hydrogen sensing response of 1.41 × 106 (under a 1% H2/air gas), a very low detecting level of 1 ppm H2/air, and a relatively shorter response (recovery) time of 201 s (26) s. Moreover, first order differential (FOD) and shape-preserving piecewise cubic interpolation (SPPCI) were also employed to overcome the wireless transmission problem for the Internet of Things (IoTs). Furthermore, based on the thermodynamic analysis, the surface coverage performance was studied for this device. As the result, the studied device exhibited practically adsorption with hydrogen gas at 200 °C. The studied device is therefore promising for high-performance hydrogen sensing applications.

A high-power GaN-based light-emitting diode (LED) with an inductively coupled plasma (ICP)-transferred nanohemispherical hybrid backside reflector is studied. A self-assembled 100 ± 5 nm SiO2 nanosphere monolayer is drop-coated on the backside of a sapphire substrate as a mask to transfer nanohemispherical patterns onto the backside of the sapphire substrate by ICP. Nanohemispherical patterns could be transferred to the deposited backside reflector. Thus, reflected photons could be redirected and scattered into arbitrary directions for light extraction. As compared with a conventional LED without a backside reflector, at 350 mA, the studied device exhibits a 118.2% enhancement in light output power without the degradation of electrical properties. Note that the adhesion between an ICP-transferred sapphire substrate and the hybrid backside reflector is better than when directly inserting an SiO2 nanosphere monolayer in the device. Thus, the process yield could be enhanced for applying in the solid-state lighting.

In this article the characteristics of In0.49Ga0.51P/GaAs/GaAs0.975Bi0.025 and In0.49Ga0.51P/GaAs heterojunction bipolar transistor (HBTs) are demonstrated and compared by two-dimensional simulated analysis. As compared to the traditional InGaP/GaAs HBT, the studied InGaP/GaAs/GaAsBi HBT exhibits a higher collector current, a lower base-emitter (B–E) turn-on voltage, and a relatively lower collector-emitter offset voltage of only 7 mV. Because the more electrons stored in the base is further increased in the InGaP/GaAs/GaAsBi HBT, it introduces the collector current to increase and the B–E turn-on voltage to decrease for low input power applications. However, the current gain is slightly smaller than the traditional InGaP/GaAs HBT attributed to the increase of base current for the minority carriers stored in the GaAsBi base.

An enhancement-mode PHEMT (EPHEMT), fabricated by Electroless Plating (EP) and gate-sinking approaches, is comprehensively studied under high-temperature ambiences (300–475 K). The interdiffusion at Pd/AlGaAs interface confirmed by Auger depth spectroscopy (AES) profile analysis leads to the modulation of threshold voltage. In addition, the corresponding Pd-gate morphologies are examined through atomic force microscopy (AFM) and scanning electron microscopy (SEM). By gate-sinking (525 K), an EP-based PHEMT with threshold voltage shifting of +0.33 V is converted to an E-mode operation. Based on inherent advantages of EP-gate formation, the studied EPHEMT shows excellent DC performance and well thermal stability. With a gate dimension of 1 × 100 μm 2 , the studied EPHEMT presents low gate current of 6.5 (74.5) μA/mm, maximum extrinsic transconductance of 185.2 (150.6) mS/mm, maximum drain saturation current of 219.9 (98.8) mA/mm, and threshold voltage of 0.203 (0.196) V at 300 (475) K. In addition, the thermal stabilities on gate current, extrinsic transconductance, and drain current are found for the studied EPHEMT. Furthermore, a designed direct-coupled FET logic (DCFL) inverter, combined with an EP-gate and a thermal evaporated (TE)-gate PHEMT, is achieved and characterized.

DC performance of GaAsSb/InGaAs type-II and InP/InGaAs type-I doped-channel field-effect transistors (DCFETs) is demonstrated and compared by two-dimensional simulated analysis. As compared with the traditional InP/InGaAs DCFET, the GaAsSb/InGaAs DCFET exhibits a higher drain current of 8.05 mA, a higher transconductance of 216.24 mS/mm, and a lower gate turn-on voltage of 0.25 V for the presence of a relatively large conduction band discontinuity (ΔE c ≈ 0.4 eV) at GaAsSb/InGaAs heterostructure and the formation of two-dimensional electron gas in the n +-InGaAs doping channel. However, due to the tunneling effect under large gate-to-source bias, it results in considerably large gate leakage current in the GaAsSb/InGaAs DCFET.

In this article, the characteristics of the GaAs homojunction camel-like gate field-effect transistors with and without the gate-to-source and gate-to-drain recesses structures are first investigated and compared. As to the device without the recesses structure, a second channel within the n+-GaAs cap layer is formed at large gate bias, which could enhance the drain output current and transconductance. Furthermore, a two-stage relationship between drain current (and transconductance) versus gate voltage is observed in the recesses structure. The simulated results exhibit a maximum drain saturation current of 447 (351 mA/mm) and a maximum transconductance of 525 (148 mS/mm) in the studied device without (with) the recesses structure. Consequentially, the demonstration and comparison of the variable structures provide a promise for design in circuit applications.

In this article, the characteristics of InP/InGaAs heterostructure-emitter bipolar transistors with 30 n-InP layer tunneling layers and a five-period InP/InGaAs superlattice are demonstrated and comparatively investigated by experimentally results and analysis. In the three devices, a 200 A n-In0.53Ga0.47As layer together with an n-InP tunneling emitter layer (or n-InP/n-InGaAs superlattice) forms heterostructure emitter to decrease collector-emitter offset voltage. The results exhibits that the largest collector current and current gain are obtained for the tunneling transistor with a 30 A n-InP tunneling emitter layer. On the other hand, some of holes injecting from base to emitter will be blocked at n-InP/n-InGaAs heterojunction due to the relatively small hole transmission coefficient in superlattice device, which will result in a considerable base recombination current in the n-InGaAs layer. Therefore, the collector current and current gain of the superlattice device are the smallest values among of the devices.

Enhanced light extraction efficiency (LEE) of high-power GaN-based light-emitting diodes (LEDs) is achieved by inserting a self-assembled SiO2 nanosphere monolayer between the substrate and backside reflectors. Due to the presence of concave surfaces and photonic crystal-like air voids, downward photons emitted from multiple quantum well toward 3-D backside reflectors, could be reflected, scattered, and redirected into arbitrary directions for light extraction. These textured 3-D backside reflectors with an SiO2 nanosphere monolayer could also extract the lateral light inside device into the normal direction and improve LEE. As compared with a conventional LED without a backside reflector and an LED with a planar hybrid backside reflector, at 350 mA, the studied device with a 3-D hybrid backside reflector exhibits 136.4% (165%) and 23.6% (27.4%) enhancements in light output power (luminous flux) without the degradation of electrical properties. Higher light intensities in light emission mapping image and far-field pattern are also obtained. These results show that a textured 3-D backside reflector could be easily formed by inserting an SiO2 nanosphere monolayer to significantly enhance the performance of high-power GaN-based LEDs.

In the InP/InGaAs metamorphic co-integrated heterostructure bipolar and field-effect transistors (BiFETs), the field-effect transistor (FET) with pseudomorphic channel layer was stacked on the top of the metamorphic heterostructure bipolar transistor (HBT) with pseudomorphic base–emitter spacer layers. In the FET, a relatively thin as well as heavily doped In0.65Ga0.35As pseudomorphic channel layer between two undoped InP layers was employed to enhance the gate forward operation voltage, drain current, and transconductance, simultaneously. On the other hand, after removing the top four layers of material structures, the studied HBT was fabricated on the metamorphic buffer layer. In the metamorphic HBT, the valence band discontinuity at InP/In0.65Ga0.35As heterojunction and emitter injection efficiency could be further extended than the conventional InP/In0.53Ga0.47As lattice-matched HBTs. Furthermore, the delta doping layer between two In0.65Ga0.35As spacer layers at emitter side could effectively eliminate the potential spike at base–emitter junction for reducing the collector–emitter offset voltage. Consequently, the co-integrated metamorphic devices show a good potential for mixed signal integrated circuits and systems applications.

Based on the InAlAs/InGaAs heterostructure doping-channel field-effect transistors (DCFETs), three co-integrated devices are demonstrated. After removing some material layers, the enhancement/depletion-mode devices and inverter logic were formed. The InAlAs/InGaAs co-integrated structures consist of an enhancement-mode device with single channel and two depletion-mode devices with double and triple channels, respectively. The insertion of an undoped large energy-gap layer between the metal gate and active channels can improve the gate breakdown voltage and turn-on voltage. Besides, by the studied integrated DCFETs two transfer characteristics are implemented for direct-coupled FET logic (DCFL) circuit applications as compared to the previous reports with only single logic transfer characteristic. Consequently, the integrated AlInAs/GaInAs DCFETs provide a promise for signal amplification and multiple inverter logic applications.

In this article, the influence of InGaAsP spacers inserted at base-collector (B-C) junction in the InP/In0.53Ga0.47As double heterojunction bipolar transistors is demonstrated by two-dimensional semiconductor simulation. Due to the addition of an InGaAsP spacer layer, two small potential spikes are formed at B-C junction and the current blocking effect is reduced. The results exhibit that the maximum current gain increases from 30 to 374 (375) as the thickness of InGaAsP spacer layer varies from 0 to 100 A (300 A). On the other hand, the device with a thicker spacer layer (300 A) could effectively improve the knee effect of the current-voltage curves as compared the other devices. In addition, the collector-emitter offset voltages less than 10 mV are observed in the three devices.

A GaN-based light-emitting diode (LED) with an aluminum (Al) reflecting and an SiO2 insulating layers (RILs) deposited on the naturally textured p-GaN surface is fabricated and studied. The use of RIL could enhance the current spreading performance and reduce the photon absorption by the p-pad metal. The textured surface is used to limit the total internal reflection and increase photon scattering. In this paper, effects of the use of an Al RL and/or an SiO2 insulating layer on the performance of GaN-based LEDs are systematically studied and compared in detail. At 20 mA, as compared with a conventional LED with naturally textured (planar) p-GaN surface, the studied device exhibits 12.2% (55.5%) enhancement in light output power. Additionally, a 28.5% (95%) increment of luminous flux is achieved. The studied device also shows 15.6% light intensity improvement of far-filed pattern. Experimentally, although power consumption and junction temperature are slightly increased because of the insertion of RIL structure, these drawbacks could be surpassed by the mentioned optical improvements. Therefore, for conventional GaN-based LEDs, light extraction efficiency could be further improved by the employment of RIL structure.

In this paper, the characteristics of InP/InGaAs abrupt, setback, and heterostructure-emitter heterojunction bipolar transistors (HBTs) are comparatively investigated by twodimensional simulation analysis. In the setback (heterostructure-emitter) HBT, a thin 50 A undoped In0.53Ga0.47As (n-In0.53Ga0.47As) layer is inserted between n-InP emitter and p+-InGaAs base layers to lower the energy band at emitter side for decreasing the collector-emitter offset voltage. The simulated results exhibits that the abrupt HBT has the largest current gain, the largest collector-emitter offset voltage, and the smallest unity gain cutoff frequency. While, the setback and heterostructure-emitter HBTs exhibit the smallest current gain and offcet voltage, respectively. Consequentially, the demonstration and comparison of the three-type HBTs provide a promise for design in circuit applications.

Based on the employments of an InGaP/GaAs superlattice emitter and a thin InGaAs pseudomorphic base structure, the device with excellent transistor action and multiple S-shaped negative-differential-resistance (NDR) switching behavior are achieved. Under normal transistor operation mode, the tunneling electrons could easily transport from InGaP/GaAs superlattice over the n-GaAs emitter layer into the thin InGaAs pseudomorphic base region for reducing the base–emitter turn-on voltage and promoting the current gain. In particular, an interesting multiple S-shaped NDR behavior is observed under inverted operation mode due to the avalanche multiplication and confinement effect for electrons at the interface between superlattice and emitter layer, respectively. As an appropriate voltage source and a load resistor are applied, three stable operation points are obtained.

Excellent dc performance of an InP/InGaAs metamorphic δ-doped heterojunction bipolar transistor (HBT) using a linearly graded In x Ga 1 − x P metamorphic buffer layer grown on GaAs substrate is demonstrated. The employment of a δ-doped sheet between two undoped spacer layers could eliminate the potential spike at base–emitter junction and increase the effective barrier, which could prevent the hole injection from base into emitter. A maximum current gain of 255, a low offset voltage of 105 mV, and a small second (third) harmonic distortions of 0.545 (− 0.05) at V CE = 2.5 V are obtained. The current gain and offset voltage are the best values than that of the previous InP/InGaAs metamorphic HBT.

Influence corresponding to the position of δ-doped supplied layer on InGaP/GaAs high electron mobility transistors is comparatively studied by two-dimensional simulation analysis. The simulated results exhibit that the device with lower δ-doped supplied layer shows a higher gate potential barrier height, a higher saturation output current, a larger magnitude of negative threshold voltage, and broader gate voltage swing, as compared to the device with upper δ-doped supplied layer. Nevertheless, it has smaller transconductance and inferior high-frequency characteristics in the device with lower δ-doped supplied layer. Furthermore, a knee effect in current-voltage curves is observed at low drain-to-source voltage in the two devices, which is investigated in this article.

Excellent characteristics of an InGaP/GaAs tunneling heterostructure-emitter bipolar transistor (T-HEBT) are first demonstrated. The insertion of a thin n-GaAs emitter layer between tynneling confinement and base layers effectivelty eliminates the potential spike at base-emitter junction and reduces the collector-emitter offset voltage, while the thin InGaP tunneling confinement layer is employed to reduce the transporting time across emitter region for electrons and maintain the good confinement effect for holes. Experimentally, the studied T-HEBN exhibits a maximum current gain of 285, a relatively low offset voltage of 40 mW, and a current-gain cutoff frequency of 26.4 GHz.

Interesting pseudomorphic high electron mobility transistors using an electrophoretic deposition (EPD) approach are fabricated and studied. Due to the low-temperature deposited gate structure, the studied device exhibits enhanced performance with less thermal damages and improved Schottky contact properties by EPD approach. In comparison with a thermal evaporation (TE) device, the higher turn-on voltage, lower gate current, and lower interface state density are observed for the EPD device. For the gate dimension of 1 × 100 μm2 the EPD device shows the higher maximum drain saturation current of 242.2 (231.9) mA/mm and excellent maximum extrinsic transconductance of 151.6 (132.5) mS/mm at 300 (420) K. Besides, the EPD device presents a comparable RF performance as compared with the TE one. Due to the improved device performance and advantages of low cost, simple process, flexible deposition on varied substrate, and adjustable metal grain size, the reported EPD approach shows the promise for high-performance device applications.

High-performance InP/GaAsSb double heteroj unction bipolar transistor (DHBT) employing GaAsSb/lnGaAs superlattice-base structure is demonstrated and compared with GaAsSb bulk-base structure by two-dimensional simulation analysis. The proposed device exhibits a higher current gain of 257 than the conventional InP/GaAsSb type-II DHBT with a lower current gain of 180, attributed to the tynneling behavior of minority carriers in the GaAsSb/lnGaAs superlattice-base region under large forward base—emitter bias. In addition, a larger unity gain cutoff frequency of 19.1 GHz is botained for the superlattice-base device than that of 17.2 GHz for the bulk-base device.

In this paper, high device linearity and characteristics of an InGaP/GaAs/InGaAs camel-like gate delta-doped p-channel field-effect transistor is demonstrated. The energy band and hole distribution are depicted with respect to the device performance. Due to the npn depletion of the camel-like gate structure, the considerable conduction band discontinuities at n + -InGaP/p-GaAs and p-GaAs/i-In 0.15 Ga 0.85 As heterojunctions, and the good confinement effect for holes in InGaAs quantum well, a large gate turn-on voltage is achieved. The drain saturation current linearly increases with the gate voltage and the high device linearity is illustrated by fitting the drain current versus the gate voltage. The excellent performance of the studied device is promise for linear amplifiers and high-frequency circuit applications.

InGaP/InGaAs doped-channel direct-coupled field-effect transistor logic (DCFL) with relatively low supple voltage is demonstrated by two-dimensional analysis. In the integrated enhancement/depletion-mode transistors, subband and two-dimensional electron gas (2DEG) are formed in the InGaAs strain channels, which substantially increase the channel concentration and decrease the drain-to-source saturation voltage. The integrated devices show high turn-on voltage, high transconductance, broad gate voltage swing, and excellent high frequency performance, simultaneously. Furthermore, the integrated devices exhibit large noise margins for DCFL application with low supply voltage of 1.5 V attributed from the relatively small saturation voltages of the studied integrated devices.

This paper reports on new GaN sensors using a Pd-mixture-Pd triple-layer sensing structure to enhance their sensitivity to hydrogen at the tens of ppm level. The proposed hydrogen sensor biased with a constant voltage produced relatively high sensing responses of ∼4.84 × 10 5 % at 10,100 ppm and ∼8.7 × 10 4 % at 49.1 ppm H 2 in N 2 . The corresponding barrier height variations are calculated to be 220 and 168 mV. When the sensor is biased by a constant current with maximum power consumption of 0.4 mW, a sensing voltage as an output signal showed a voltage shift of more than 17 V (the highest value ever reported) at 49.1 ppm H 2 in N 2 . By comparison to Pd-deposited GaN sensors, the improvement in static-state performance is likely attributed to double dipole layers formed individually at the Pd–GaN interface and inside the mixture. Moreover, voltage transient response and current transient response to various hydrogen-containing gases were experimentally studied. The new finding is that the former response time is shorter than the latter one.

This paper reports on a new Pd/GaN hydrogen sensor with two multi-finger Schottky contacts (named metal–semiconductor–metal (MSM) hydrogen sensor). Effects of hydrogen absorption on the MSM sensor are investigated. In addition to comparisons of sensing mechanism between metal–semiconductor (MS) and MSM sensors, related current–voltage characteristics, sensor responses, Schottky barrier height variations, response transients, and switching behaviors are included. Experimentally, symmetrically bi-directional sensing performances are obtained in the newly designed MSM sensor, resulting in both widespread forward- and reverse-voltage-operating regimes. When the MSM sensor is measured in a 1080 ppm H2/N2 ambience, the voltage-independent response and barrier-height variation obtained are 51 and 102 mV, respectively. Furthermore, the measured response time is as short as 38 ± 2 s. Together with good switching behaviors, the MSM sensor studied is a promising candidate as a high-performance hydrogen sensor being easily integrated with other devices.

The breakdown behaviors of InP/InGaAs single heterojunction bipolar transistor (SHBT) and double heterojunction bipolar transistor (DHBT) are studied and demonstrated. By using a composite collector structure at the base–collector heterojunction, the undesired current-blocking effect, switching, hysteresis phenomenon usually found in an InP/InGaAs conventional DHBT are not observed in our DHBT device. Experimentally, as compared with the studied SHBT, the studied DHBT reveals the enhanced breakdown voltages, lower collector leakage current I CO , and smaller electron impact ionization α . Moreover, the temperature-dependent electron impact ionization characteristics and electrical reliability for both devices are also studied. Therefore, the studied DHBT device provides the promise for millimeter-wave and power circuit applications.

New metal-semiconductor-metal hydrogen sensors are fabricated to take advantages of symmetrically bidirectional detection. Unlike commonly used single catalytic metal layers, a mixture of Pd and SiO2 inserted between Pd and GaN was employed as sensing media. There are three sensing regions (i.e., 2-D dipole, transient, and 3-D dipole regions) observed in static response. Room-temperature sensitivity larger than 107 was obtained in 1080-ppm H2/N2 ambient. The barrier-height variation is as high as 422 mV. To our best knowledge, these are the highest values ever reported. According to transient response, a short response time of 70 s is obtained at room temperature. Thus, a newly developed concept of forming 3-D dipoles is introduced to possibly explain experimental results.

The characteristics of InGaP/GaAs heterostructure-emitter bipolar transistors (HEBTs) including conventional GaAs bulk base, InGaAs/GaAs superlattice-base, and InGaAs quantum-well base structures are presented and compared by two-dimensional simulation analysis. Among of the devices, the superlattice-base device exhibits a highest collector current, a highest current gain and a lowest base–emitter turn-on voltage attributed to the increased charge storage of minority carriers in the InGaAs/GaAs superlattice-base region by tunneling behavior. The relatively low turn-on voltage can reduce the operating voltage and collector–emitter offset voltage for low power consumption in circuit applications. However, as to the quantum-well base device, the electrons injecting into the InGaAs well are blocked by the p+-GaAs bulk base and it causes a great quantity of electron storage within the small energy-gap n-type GaAs emitter layer, which significantly increases the base recombination current as well as degrades the collector current and current gain.

The dc performances of an InP/InGaAs pnp heterostructure-emitter bipolar transistor are investigated by theoretical analysis and experimental results. Though the valence band discontinuity at the InP/InGaAs heterojunction is relatively large, the addition of a heavily-doped as well as thin p +-InGaAs emitter layer between p-InP confinement and n +-InGaAs base layers effectively eliminates the potential spike at emitter-base junction and simultaneously lowers the emitter-collector offset voltage and increases the potential barrier for electrons. Experimentally, a high current gain of 88 and a low offset voltage of 54 mV have been achieved.

The device and inverter characteristics based on InGaP/InGaAs n- and p-channel complementary pseudomorphic doped-channel HFETs are demonstrated. Particularly, the saturation voltage of the n-channel device is substantially reduced because the two-dimensional electron gas (2DEG) is formed and modulated in the InGaAs strain channel. Experimentally, an extrinsic transconductance of 109 (11.5) mS/mm and a saturation current density of 32.5 (−27) mA/mm are obtained for the n-channel (p-channel) device. Furthermore, the noise margins NMH and NML values are up to 1.317 and 0.28 V, respectively, at a supply voltage of 2.0 V for complementary logic inverter application.

The temperature-dependent dc characteristics and noise performance of an interesting InGaP/GaAs heterojunction bipolar transistor (HBT) with emitter ledge passivation are demonstrated. Experimentally, due to the emitter ledge passivation, higher current gains and wider collector current over the measured temperature range (300–400 K) are observed as compared to a conventional device. In addition, the studied device exhibits lower base current ideality factors, better thermal stabilities on dc current gains, lower base surface recombination current densities and improved device reliability. Therefore, the studied device is suitable for low-power and high-temperature electronic applications.

In this paper, an interesting thermally stable In0.42Al0.58As/In0.46Ga0.54As metamorphic high electron mobility transistor (MHEMT) is fabricated and investigated. Good dc and RF characteristics are obtained by precisely depositing gold (Au) upon the In0.42Al0.58As barrier layer as the Schottky contact metal. For a MHEMT with gate dimensions of 1 × 100 µm2, high gate–drain breakdown voltage, high turn-on voltage, low gate leakage current density, high maximum transconductance with broad operating regime and low output conductance are obtained even at ambient temperatures up to 510 K (240 °C). The studied device also shows a very good microwave performance at room temperature. Moreover, the relatively low variations of the device performance are achieved over a wide temperature range (from 300 to 510 K). Therefore, the studied device has a good thermally stable performance that is suitable for high-speed and high-power electronic applications.

In this paper, extremely high potential barrier height and gate turn-on voltage in an n+/p+/n+/p+/n GaAs field-effect transistor employing double camel-like gate structures are demonstrated. The gate potential barrier height of the double camel-like gate is substantially enhanced by the addition of another n+/p+ layer in the gate region, as compared with the conventional n+/p+/n single camel-like gate structure. The influence of gate structure layers on the depletion depth, potential barrier height, transconductance and gate voltage swing are addressed. Experimental results show that a relatively high gate turn-on voltage up to +4.9 V is realized because two reverse-biased junctions of the double camel-like gate structures absorb part of the positive gate voltage. In addition, an extremely broad gate voltage swing greater than 4.6 V with the transconductance above 100 mS mm?1 is observed. These results indicate that the studied device is suitable for linear and signal amplifiers and inverter circuit applications.