1. Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2m).
- Author
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Rahaman, H., Mathew, J., Pradhan, D.K., and Jabir, A.M.
- Subjects
- *
ELECTRONIC circuit design , *LOGIC design , *ELECTRONIC circuits , *COMPUTER circuits , *COMPUTER networks , *ELECTRONIC data processing - Abstract
This paper presents an algebraic testing method for detecting stuck-at faults in the polynomial-basis (PB) bit-parallel (BP) multiplier circuits over GF(2m). The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of the ATPG tool. This low- complexity testing method requires (2m + 1) test vectors for detecting single stuck-at faults in the AND part and multiple stuck-at faults in the EXOR part of the multiplier circuits. The test vectors are independent of the multiplier's structure, as proposed in (11), but are dependent on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100 percent single stuck-at fault coverage. [ABSTRACT FROM AUTHOR]
- Published
- 2008
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