Search

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

Very Large Scale Integration (VLSI) based neuromorphic circuits also known as Silicon Neurons (SiNs) emulate the electrophysiological behavior of biological neurons. With the advancement in technology, neuromorphic systems also lead to various reliability issues and hence making their study important. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are the two major reliability issues present in VLSI circuits. In this work, we have investigated the combined effect of BTI and HCI on the two types of integrate-and-fire based SiNs namely (a) Axon-Hillock and (b) Simplified Leaky integrate-and-fire circuits using their key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. Proposed reliability-aware designs show negligible deviation in performance parameters after aging. The time-zero process variability analysis is also carried out for proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.

With the continuous scaling of CMOS technology and growing density of circuit chips, accurate and efficient calculation of reliability for integrated circuits is becoming a critical issue. One of major obstacles in calculating the reliability efficiently with high accuracy is the difficulty in dealing with reliability correlations among signals. This paper proposes an analytical model to estimate the correlations using structural and probabilistic information within a local area of circuits, as well as to propagate the correlations throughout the circuit in a topological order of logic gates, which makes the computation time linear to circuit size. Simulations show that the resulting percentage errors in estimating output reliabilities are less than 2%.

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on area, power, performance and stability is analyzed showing that the most affected parameter is read stability, although this impact can be overcome using some of the read assist circuits proposed in the literature. The main benefits are layout regularity enhancement, with its consequent higher tolerance to variability, cell area reduction by 25 percent (with respect to a cell having a cell ratio of 2), leakage current improvement by a 35 percent, as well as energy dissipation reduction and a soft error rate per bit improvement of around 30 percent.

Copyright IEEE, The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-Aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples., This work was supported by the VIGILANT Project (PID2019-103869RB / AEI / 10.13039/501100011033) and the TEC2016-75151-C3-R Project (AEI/FEDER, UE).

With the introduction of FinFET transistors, the Self-Heating Effect (SHE) became a major reliability challenge. In this work, we present an automated SHE estimation method integrated within a circuit reliability framework. It allows designers to study SHE in analogue and digital circuits. For accurate analysis, we employ electrically and thermally calibrated 14nm FinFET transistor models. To demonstrate the capabilities of our framework, we study SHE in standard cells and report a considerable dependence on the cell topology. We show how SHE can induce 15% delay increase in AND3 logic gate, highlighting the importance of taking SHE into account. Otherwise, reliability cannot be sustained during the circuit’s operation.

Due to the aggressive scaling of transistor dimensions, which took place in the last decades, chip devices are exposed to high electric fields and current densities during normal operation. These working conditions trigger degradation phenomena that compromises the device functionality and rises questions regarding circuit reliability. In this paper we present a simulation based methodology that incorporates the aging phenomena, which might allow to address the reliability aspects during the design phase and pave the way for further life-time projections at the design stage. Piecewise-linear functions are used to model the propagation delays and estimate the correlation between the different degradation mechanisms and the PVT variations.

In-memory computing architectures based on Resistive random access memory technologies (RRAM) are a promising candidate for the development of ultra-low power hardware accelerators that could enable the deployment of deep neural networks inference algorithms on energy constrained devices at the edge of the communication network. However, the study of the reliability of such circuits is non-trivial due to the intrinsic RRAM devices nonlinearity and stochasticity. For instance, RRAM devices are subject not only to device-to-device and cycle-to-cycle resistance variations but also to Random Telegraph Noise which introduces additional time dependent resistance fluctuations that could result in reduced circuit performance. Previous studies exploited simplified statistical models to show that such device nonidealities may reduce the classification accuracy even when binarized neural networks are employed. However, a circuit reliability analysis based on full circuit-level simulations is still missing. In this work, we develop and train a low-bit precision neural network which employs binary weights and 4-bits activations. We further analyze the impact of RRAM nonidealities (e.g., variability and Random Telegraph Noise) on the classification accuracy by means of full circuit-level simulations enabled by a physics-based RRAM compact model, calibrated on experimental data from the literature. Results show that combining binary weights with low-precision activations allows retaining software-level accuracy even in the presence of Random Telegraph Noise and weight variability.

This review paper reports the prerequisites of a monolithic integrated terahertz (THz) technology capable of meeting the network capacity requirements of beyond-5G wireless communications system (WCS). Keeping in mind that the terahertz signal generation for the beyond-5G networks relies on the technology power loss management, we propose a single computationally efficient software design tool featuring cutting-edge optical devices and high speed III–V electronics for the design of optoelectronic integrated circuits (OEICs) monolithically integrated on a single Indium-Phosphide (InP) die. Through the implementation of accurate and SPICE (Simulation Program with Integrated Circuit Emphasis)-compatible compact models of uni-traveling carrier photodiodes (UTC-PDs) and InP double heterojunction bipolar transistors (DHBTs), we demonstrated that the next generation of THz technologies for beyond-5G networks requires (i) a multi-physical understanding of their operation described through electrical, photonic and thermal equations, (ii) dedicated test structures for characterization in the frequency range higher than 110 GHz, (iii) a dedicated parameter extraction procedure, along with (iv) a circuit reliability assessment methodology. Developed on the research and development activities achieved in the past two decades, we detailed each part of the multiphysics design optimization approach while ensuring technology power loss management through a holistic procedure compatible with existing software tools and design flow for the timely and cost-effective achievement of THz OEICs., Applied Sciences, 11 (5), ISSN:2076-3417

With the CMOS technology scaling, transistor aging has become one major issue affecting circuit reliability and lifetime. There are two major classes of existing studies that model the aging effects in the circuit delay. One is at transistor-level, which is highly accurate but very slow. The other is at gate-level, which is faster but less accurate. Moreover, most prior studies only consider a limited subset or limited value ranges of aging factors. In this paper, we propose Aadam, a fast, accurate, and versatile aging-aware delay model for generic cell libraries. In Aadam, we first use transistor-level SPICE simulations to accurately characterize the delay degradation of each library cell under a versatile set of aging factors, including both physical parameters (i.e., initial threshold voltage and transistor width/length ratio) and operating conditions (i.e., working temperature, signal probability, input signal slew range, output load capacitance range, and projected lifetime). For each library cell, we then train a feed-forward neural network (FFNN) to learn the relation between the input aging factors and output cell delay degradation. Therefore, for a given input circuit and a given combination of aging factors, we can use the trained FFNNs to quickly and accurately infer the delay degradation for each gate in the circuit. Finally, to effectively estimate the aging-aware lifetime delay of large-scale circuits, we also integrate Aadam into a state-of-the-art static timing analysis tool called OpenTimer. Experimental results demonstrate that Aadam achieves fast estimation of the aging-induced delay with high accuracy close to transistor-level simulation.

Nanoscale digital integrated circuits are getting increasingly vulnerable to soft errors due to aggressive technology scaling. Hence, SER estimation of combinational circuits has been one of the challenges of circuit reliability analysis due to three masking effects. On the other hand, as technology scales further, variations in cell geometries become prominent, as well. According to recent reports, the reliability of a particle strike-induced transient fault for a cell is sensitive to its geometry size, especially to transient faults which induce small charges. Therefore, both process variation impact and soft error effect need to be integrated for accurately estimating SER of nanoscale circuit designs. The impacts of process variations on the characteristics of circuits in nano era make statistical approaches an unavoidable option for SER estimation procedure. In this chapter, we present a statistical SER estimation framework. We introduce a concept called statistical vulnerability window (SVW) which is a unified variation-aware inference of various constraints necessary for a SET to cause soft errors in the circuit considering all three masking factors. Using a level-order backward traversal, SVWs for each circuit gate output are calculated using a computation model. The statistical SER of the circuit is gradually estimated considering a mathematical formulation of SER based on SVW parameters.

Circuit reliability is a significant concern in scaled technologies. Physical aging models derived by DC stress on discrete devices are accurate to an extent, but can be further improved by evaluating the behaviour of simple circuits such as ring oscillators (RO). In this work, we establish correlation between individual device degradation to circuit’s figure of merit (frequency degradation) to refine understanding of the predictive ability of DC models. We further present novel re-configurable circuits that enables different waveform scenarios seen in design to bridge gaps between DC-stressed device aging and complex circuits. Unique features of this work include: (1) Correlating discrete device degradation to circuit performance degradation, (2) development of a novel PMOS/NMOS aging isolator circuit (PNI) which can isolate the aging contribution of a single device type, and (3) development of a state-of-art re-configurable circuit that modulate waveforms to customize the aging contribution from any particular physical mechanism (NBTI, PBTI, N-HCI or P-HCI).

For the first time, we present a study of BTI and HCD degradation in a 32 × 64 cell SRAM array including Sense Amplifiers (SA), Write Drivers (WD) and pre-charging circuitry (one each for 64 columns) stimulated by the workload-induced activity of a commercial processor. In under 2 hours, our fully automated framework employs the extracted activities to create voltage waveforms used in SPICE simulations (SRAM Array, SA, WD) and degrades transistors using their individual exhibited voltages as stimuli in BTI and HCD models. We support different temperatures, supply voltages (including DVFS), SRAM, SA and WD designs.

International audience; Electronics are increasingly susceptible to energetic particle interactions within the silicon. In order to improve the circuit reliability under radiation effects, several hardening techniques have been adopted in the design flow of VLSI systems. This paper proposes a pin assignment optimization in logic gates to reduce the Single-Event Transient (SET) cross-section and improve the in-orbit soft-error rate. Signal probability propagation is used to assign the lowest probability to the most sensitive input combination of the circuit by rewiring or pin swapping. The cell optimization can reach up to 48% reduction on the soft-error rate. For the analyzed arithmetic benchmark circuits, an optimized cell netlist can achieve from 8% to 28% reduction on the SET crosssection and in-orbit soft-error rate at no cost in the circuit design area. Additionally, as the pin swapping is a layout-friendly technique, the optimization does not impact on the cell placement and it can be adopted along with other hardening techniques in the logic and physical synthesis.

The development of nanoscale technology for integrated circuit chips highlights the reliability of circuit reliability. The path formed by the basic unit of the circuit has a significant influence on the overall reliability of the circuit. Therefore, it is necessary to quickly and effectively locate the path to understand the difference in reliability between logic circuits of different structures in time. Combined with the Monte Carlo tree search strategy and based on relaxation operations, this paper realizes the rapid location of sensitive paths in the combinational circuit while ensuring the accurate location of sensitive paths.

In the past few years, Time-Dependent Variability has become a subject of growing concern in CMOS technologies. In particular, phenomena such as Bias Temperature Instability, Hot-Carrier Injection and Random Telegraph Noise can largely affect circuit reliability. It becomes therefore imperative to develop reliability-aware design tools to mitigate their impact on circuits. To this end, these phenomena must be first accurately characterized and modeled. And, since all these phenomena reveal a stochastic nature for deeply-scaled integration technologies, they must be characterized massively on devices to extract the probability distribution functions associated to their characteristic parameters. In this work, a complete methodology to characterize these phenomena experimentally, and then extract the necessary parameters to construct a Time-Dependent Variability model, is presented. This model can be used by a reliability simulator.

Fast Orbit Feedback System (FOFB) can be installed in a synchrotron light source to eliminate undesired disturbances and to improve the stability of beam orbit. The design and implementation of an accurate and reliable Fast Corrector Power Supply (FCPS) is essential to realize the effectiveness and availability of the FOFB. A reliability assessment for the FCPSs in the FOFB of Taiwan Photon Source (TPS) considering MOSFETs’ temperatures is represented in this paper. The FCPS is composed of a full-bridge topology and a low-pass filter. A Hybrid Pulse Width Modulation (HPWM) requiring two MOSFETs in the full-bridge circuit to be operated at high frequency and the other two be operated at the output frequency is adopted to control the implemented FCPS. Due the characteristic of HPWM, the conduction loss and switching loss of each MOSFET in the FCPS is not same. Two of the MOSFETs in the full-bridge circuit will suffer higher temperatures and therefore the circuit reliability of FCPS is reduced. A Modified PWM Scheme (MPWMS) designed to average MOSFETs’ temperatures and to improve circuit reliability is proposed in this paper. Experimental results measure the MOSFETs’ temperatures of FCPS controlled by the HPWM and the proposed MPWMS. The reliability indices under different PWM controls are then assessed. From the experimental results, it can be observed that the reliability of FCPS using the proposed MPWMS can be improved because the MOSFETs’ temperatures are closer. Since the reliability of FCPS can be enhanced, the availability of FOFB can also be improved.

Emerging nanoscale computing structure quantum-dot cellular automata (QCA) is evolving as a possible replacement for complementary metal–oxide–semiconductor technology in near future. Being a new technology, it is prone to various types of fabrication-related faults and process variations. So, QCA-based circuits are prone to errors, and therefore pose significant reliability-related issues. Hence, there is an emerging need to design fault-tolerant QCA-based circuits to mitigate the reliability issues. This study first presents QCA-based new designs of 2-input Exclusive-OR gate and 1 bit full adder using conventional design approach without redundant QCA cells. Then, the fault tolerance has been implemented in these designs by introducing redundant QCA cells. The proposed circuits exhibit significant improvements in fault-tolerant capability against cell omission, misalignment, displacement, and extra cell deposition defects. The proposed fault-tolerant designs have been compared with existing designs in terms of generalised design metrics of QCA circuits. Energy dissipation results have been computed for the proposed fault-tolerant circuits using accurate QCAPro power estimator tool. Influence of temperature variations on the polarisation of the proposed fault-tolerant circuits has also been investigated. The functionality of the proposed circuits has been verified with QCADesigner version 2.0.3 tool.

Due to aggressive technology scaling in electronic of digital integrated circuits, the circuit reliability is becoming an ever-increasing challenge. In nanoscale technologies, the physical and chemical properties of materials are fundamentally different compared to the larger scales. Therefore, it is necessary to revise the conventional reliability assessment techniques considering their applicability to nanoscale integrated circuits. This paper presents a method for evaluating the circuit reliability at the transistor level of abstraction considering the physical characteristics of the transistors. The proposed method considers various parameters, including the probability of different types of a transistor failure, the topology of logic gates and the logical values of the applied input vectors. Experimental results show that the proposed approach provides accurate transistor-level circuit reliability evaluations (with

In this study a careful analysis of the device and the circuit level variability and reliability are presented. Planar 20 nm System on Chip (SoC), 16 nm FinFET (16FF) and 10 nm FinFET (10FF) devices are studied to understand the time-zero process variability and Bias Temperature Instability (BTI) stress induced (time dependent) threshold voltage (VT) variations to evaluate the device degradation. Moreover, to understand the circuit level variability, the 6-Transistor (6T) SRAM performance is assessed in terms of the static noise margin (SNM) degradation under the influence of BTI stress. Finally, the product level SRAM performance is studied in terms of the minimum SRAM operating voltage (Vmin) degradation.

With the downscaling of CMOS devices, dynamic variability induced by negative bias temperature instability (NBTI) has become a critical issue. In addition to the time-dependent device-to-device variation (DDV) of NBTI degradation, the cycle-to-cycle variation (CCV) originated from random trap occupation is found non-negligible and should be added into the total dynamic variation. This paper summarizes our recent studies on NBTI-induced dynamic variability, focusing on the CCV effect, with more details on the statistical modeling, circuit reliability simulation methodologies and experimental results. By adding the random trap occupation into consideration, a statistical model for total dynamic variation (DDV + CCV) is proposed. The effective occupancy probability peff is introduced as a key parameter for modeling and circuit reliability simulation. With the statistical trap response (STR) method and modified on-the-fly method, the proposed model is validated by the experimental evidence under both DC and AC NBTI. According to the model and experimental results, circuit reliability simulation framework is proposed for both long-term quasi-static and short-term transient performance evaluation with the additional impact of CCV. Two representative digital circuit units, ring oscillator (RO) and SRAM cell, are simulated under different conditions, indicating it necessary to consider the evident influence of the CCV in accurate circuit reliability evaluation. The results are helpful for the reliability/variability-aware circuit design in nanoscale technology.

Pulsed latches are gaining increased visibility in low-power ASIC designs. They provide an alternative sequential element with high performance and low area and power consumption, taking advantage of both latch and flip-flop features. While the circuit reliability and robustness against different process, voltage, and temperature variations are considered as critical issues with current technologies, no significant reliability study was proposed for pulsed latch circuits. In this paper, we present a study on the effect of different PVT variations on the behavior of pulsed latches, considering the effect on both the pulser and the latch. In addition, two novel design approaches are presented to enhance the reliability of pulsed latch circuits, while keeping their main advantages of high performance, low power, and small area. Experiments performed using Synopsys 28nm PDK demonstrate the ability of the proposed approaches to keep the same reliability level at different supply voltages and temperatures in the presence of process variations, with a very small area overhead of around 3%. The two proposed designs have negligible power overhead when running at nominal supply voltage, and they have higher yield per unit power when compared with the traditional design at different voltages and temperatures.

Dynamic voltage scaling (DVS) has become one of the most effective approaches to achieve ultra-low-power SoC. To eliminate timing errors arising from DVS, several error-resilient circuit design techniques were proposed to detect and/or correct timing violations. The most recently proposed time-borrowing-and-local-boosting (TBLB) technique has the advantage of lower power consumption and less performance degradation due to the needlessness of pipeline stalls. On the other hand, to make the best use of the TBLB technique, the latency from error detection to voltage boosting for TBLB latches must be carefully considered, especially during physical design. To address this issue, this paper first introduces the behavior of TBLB circuits, and then presents two major design styles of TBLB latches, including TBLB macros and multi-bit TBLB latches, for reducing detection-to-boosting latency. The corresponding physical synthesis methodologies for both design styles are further proposed. Experimental results based on the IWLS benchmarks show that the proposed physical synthesis approach for resilient circuits with multi-bit TBLB latches is very effective in reducing the delay of both combinational and error-detection circuits, which indicates better circuit reliability. To our best knowledge, this is the first work in the literature which introduces the physical synthesis methodologies for TBLB resilient circuits.

With fabrication technology reaching nano levels, systems are exposed to higher susceptibility to soft errors. Thus, development of effective techniques for designing soft error tolerant systems is of high importance. In this work, an integrated soft error tolerance technique based on logical implications and transistor sizing is proposed. In order to reduce implication learning time, a set of source and target nodes with predefined thresholds are selected and implications between these nodes are extracted. Then, the impact of adding a functionally redundant wire (FRW) due to each implication is evaluated. This is done based on identifying an implication path and the gates along the implication path whose detection probabilities will be reduced due to adding the implication FRW. Then, the gain of an implication is estimated in terms of reduction in fault detection probabilities of gates along an implication path. The implication with the highest gain is selected. The process is repeated until the gain is less than a predetermined threshold. The proposed implication-based fault tolerance technique enhances the circuit reliability with minimal area overhead based on enhancing logical masking. However, its effectiveness depends on the existence of such relations in a circuit and can enhance circuit reliability upto a certain level. To enhance circuit reliability to any required level, selective-transistor redundancy (STR) based technique is then applied. This technique is based on providing fault tolerance for individual transistors with high detection probability based on transistor duplication and sizing. Experimental results show that the proposed integrated fault tolerance technique achieves similar reliability in comparison to applying STR alone with lower area overhead.

Resistive switching memories (RRAMs) are one of the most promising alternatives for nonvolatile storage and nonconventional computing systems. However, their behavior, and therefore their reliability, is limited by technology intrinsic constraints. Standard CMOS reliability analyses do not take into account RRAM-related misbehaviors. Consequently, new and more thorough characterization approaches are needed. Even more important, as RRAM is proposed to become a key piece in aerospace solutions, new radiation and temperature analyses should also be considered in reliability-oriented methodologies. This work presents a solution that completely characterizes RRAM and CMOS hybrid circuits under the combined effects of both technology and environmental error sources. The analysis strategy is based on three pillars: the definition of suitable models, the application of user-defined metrics to measure both circuit reliability and performance, and the efficient definition of the design space. These concepts are used by a powerful simulation framework, achieving automatic characterization of RRAM-based circuits by simultaneously considering multiple error sources. As a case of study, a thorough analysis of an RRAM read driver, including RRAM lifetime, circuit temperature, CMOS and RRAM variability, and radiation—both accumulated dose and single particle impacts—highlights the proposed approach capabilities.

Current technology scaling trends aggressively increases the susceptibility of combinational circuit reliability to radiation-induced transient faults (which also known as soft errors). Various gate sizing techniques have been used to reduce soft error rate (SER) in the past, but their main drawback is that they are expensive in term of run time. These methods require changes to adapt to the large scale circuits. In this paper, an efficient circuit partitioning-based gate sizing method is presented, which significantly speeds up the gate sizing optimization process. In the proposed method, the circuit is divided into the topologically levelized small subcircuits by cone structures. Then, the subcircuits which are located in the same level are resized individually and independently. The subcircuit error probability (SEP) metric is introduced to evaluate the contribution of each subcircuit into the total circuit SER. The key idea of the proposed method is to evaluate the effects of each gate sizing on circuit reliability locally using SEP instead of global evaluation by the total circuit SER. Such evaluation results in speeding up the gate sizing optimization process. Experimental results show that the proposed approach is about 280× orders of magnitude faster than the sensitivity-based gate sizing approach [R. R. Rao, D. Blaauw, and D. Sylvester, “Soft error reduction in combinational logic using gate resizing and flipflop selection,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. , 2006, pp. 502–509] while it can achieve up to 45% reduction in circuit SER with less than 17% area overhead. This level of speed and efficiency makes the proposed approach a viable solution to mitigate the SER of very large combinational circuits used in industry.

In this study, a single-stage quasi-resonant (QR) AC–DC converter based on buck–boost and flyback circuits is proposed. The forestage buck–boost circuit works in discontinuous conduction mode to achieve a high-input power factor (PF), and the backstage flyback converter, working in QR mode, is responsible for energy transfer. The QR switch mode can improve the efficiency of the converter by decreasing the switch turn-on losses. The single-stage topology can reduce the cost and raise the reliability of the system. The detailed design process is described in this study, and a 50 W prototype was developed that has a maximum PF higher than 0.99 and a maximum efficiency of 90.91% in nominal working conditions.

With fabrication technology reaching nanolevels, systems are becoming more prone to manufacturing defects with higher susceptibility to soft errors. This paper is focused on designing combinational circuits for soft error tolerance with minimal area overhead. The idea is based on analyzing random pattern testability of faults in a circuit and protecting sensitive transistors, whose soft error detection probability is relatively high, until desired circuit reliability is achieved or a given area overhead constraint is met. Transistors are protected based on duplicating and sizing a subset of transistors necessary for providing the protection. In addition to that, a novel gate-level reliability evaluation technique is proposed that provides similar results to reliability evaluation at the transistor level (using SPICE) with the orders of magnitude reduction in CPU time. LGSynth’91 benchmark circuits are used to evaluate the proposed algorithm. Simulation results show that the proposed algorithm achieves better reliability than other transistor sizing-based techniques and the triple modular redundancy technique with significantly lower area overhead for 130-nm process technology at a ground level.

This study introduces a novel architecture for image steganography using reversible logic based on quantum dot cellular automata (QCA). Feynman gate is used to achieve the reversible encoder and decoder for image steganography. A Nanocommunication circuit for image steganography is shown using proposed encoder/decoder circuit. The proposed QCA circuits have lower quantum cost than traditional designs. It shows the cost effectiveness functionality of the proposed designs. The proposed circuit has 28.33% improvement in terms of area over complementary metal-oxide-semiconductor circuit. To perform image steganography LSB technique is used; signal-to-noise ratio (SNR), peak SNR and mean squared error (MSE) are also computed. The proposed QCA encoder/decoder circuit is suitable for reversible computing. To establish this, the heat energy dissipation by the proposed encoder/decoder circuit is estimated. The estimation shows that the encoder/decoder circuit has very low energy dissipation. Single missing/additional cell-based defect analysis is also explored in this study. Reliability of the circuit is tested against different temperatures. Implementation and testing of the circuit are achieved using QCADesigner tool. MATLAB is used to produce the input to the proposed circuit.

Heterogeneous three-dimensional (3D) integrated technique is a promising method to achieve breakthrough bandwidth between DRAM and CPU in a computer system. However, in such stacked structure, the elevated temperature poses big challenges to the circuit reliability. In this paper, we provide our solutions to three instability effects in the 3D stack: bias temperature instability, time dependent dielectric breakdown and electromigration.

Logic circuits based on Resistive RAM (RRAM) devices and the material implication logic (IMPLY) are promising solutions for low-power logic-in-memory (LiM) architectures. Still, their diffusion is limited by their high design complexity resulting from device and circuit non-idealities. These non-idealities are usually overlooked in the design phase when using simplified RRAM models, thus leading to unreliable designs. In this work, we derive correct design strategies for reliability of RRAM-based LiM circuits and quantitatively evaluate circuit performances using a physics-based compact model.

The embedded temperature sensor which monitors the hot spots of the chip had become an essential circuit for improving the reliability of the system-on-a-chip (SoC). However, most of the temperature sensors cannot resist the influence of voltage variations and results in significant temperature errors. In this paper, the relative reference modeling (RRM)-based temperature sensor is presented. The proposed temperature sensor uses a low-temperature sensitivity voltage classifier and a low-voltage sensitivity proportional to absolute temperature (PTAT) circuit to resist the voltage variations. Addition, the process variations can be eliminated after the three-point calibration. The proposed temperature sensor was fabricated in TSMC 90nm CMOS process. The measured results show that the temperature error of the proposed design is from -1.47°C to 1.40°C with supply voltage 0.9 to 1.1V.

Negative bias temperature instability (NBTI) is an significant reliability problem that can affect circuit performance. This paper presents an investigation of reliability on standard cell library circuit performance based on R-D model. Predictive Technology Model (PTM) and HSPICE MOSRA were used for circuit reliability study. Low Power (LP) PTM model of 32nm was used in this simulation. The delay time, threshold voltage and average power were investigated with the existence of the NBTI problems. The time exponent of the threshold voltage shift shows that the defect mechanisms consist of interface trap, Nit or combination of Nit and oxide trap, Not. The propagation delay increased as the aged year increased. The average power not affected due to the NBTI effect.

Time-Dependent Variability has attracted increasing interest in the last years. In particular, time-dependent phenomena such as Bias Temperature Instability, Hot Carrier Injection and Random Telegraph Noise can have a large impact on circuit reliability, and must be therefore characterized and modeled. For technologies in the nanometer range, these phenomena reveal a stochastic behavior and must be characterized in a massive manner, with enormous amounts of data being generated in each measurement. In this work, a novel tool with a user-friendly interface, which allows the robust and fully-automated parameter extraction for RTN, BTI and HCI experiments, is presented.

In the past years, the conformal coating on the printed circuit board has been widely used because it offers several advantages in terms of protection and reliability of electronic circuits. However, the coating is a dielectric material, which can impact on the performance of radio-frequency components such as microstrip filters. Hence, the coating characterisation from the dielectric point of view is essential in order to design filters that meet prefixed requirements. Although the dielectric properties of commercial conformal coatings are well known, specific analyses on the effect of the coating on devices performance for space applications are not present in the literature and the coating manufactures do not often provide an appropriate characterisation of dielectric properties, making the analysis and the design of the microstrip filters difficult. The authors discuss numerical and experimental results regarding the performance of a coupled microstrip filter and show that the presence of CV-1152 coating causes a significant shift of the S-parameters. Moreover, a new configuration of the filter based on a fractal shape is proposed, which is characterised by more compact size and an optimised bandwidth.

High voltage tole rant IO interface provides an efficient and flexible solution for integrated multimedia application. In this paper, we studied the design for reliability of IO interface in advanced technology node. Three different approaches, which is from device, layout and circuit point of view, to enhance the IO overdrive circuit (IP) reliability are investigated. We successfully develop a LDMOS that is compatible with advanced process and provides good reliability. However, new device development is a time consuming process. To reduce time-to-market, two solutions are proposed. 1) Taking the advantage of reverse body bias effect to reduce HCI damage on IP level. It can be achieved by implementing deep N-well. 2) Reducing the overstress voltage on devices by bias tracing circuit. Finally, we compared the IO interface performance and area of each solution. The solution with bias tracing circuit exhibits good reliability to sustain 5V stress and provides 66% area reduction.

This work presents measured test-data corresponding to a comprehensive reliability characterization of diode-connected MOS transistors. An array-based test structure, with the specific aim of quantifying the impact of feedback on the aging dynamics for the circuit configuration of interest was designed and implemented in a 65nm Low-Power (LP) process. Through detailed measurement data obtained using the test-vehicle we, (1) characterize the impact of feedback on the aging rate and compare it to the no-feedback case & (2) evaluate the efficacy of iterative simulations for lifetime projection in such scenarios with the method based on the universality of hot carrier degradation extended to the case featuring feedback.

Bias Temperature Instability has become a critical issue for circuit reliability. This phenomenon has been found to have a stochastic and discrete nature in nanometer-scale CMOS technologies. To account for this random nature, massive experimental characterization is necessary so that the extracted model parameters are accurate enough. However, there is a lack of automated analysis tools for the extraction of the BTI parameters from the extensive amount of generated data in those massive characterization tests. In this paper, a novel algorithm that allows the precise and fully automated parameter extraction from experimental BTI recovery current traces is presented. This algorithm is based on the Maximum Likelihood Estimation principles, and is able to extract, in a robust and exact manner, the threshold voltage shifts and emission times associated to oxide trap emissions during BTI recovery, required to properly model the phenomenon.

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS technologies for digital, analogue and RF designs. However, it has been demonstrated by several researchers that TFET circuits face increased on-state Miller capacitance effect, which leads to poor transient characteristics with large overshoots and undershoots. This would minimise the reliability of TFET circuits though energy efficient. This work gives more design insights (optimal sizing, number of stages, supply voltage) into TFET circuit reliability and proposes a TFET based circuit interaction design approach for ultra-low power and reliable ring oscillator circuit design. It has been shown that TFET circuit designs without proper reliability enhancement techniques such as circuit interaction or co-design approach exhibits very large undershoots/overshoots (∼20–50%). The proposed TFET circuit co-design approach (i.e. differential topology based design in comparison with the complementary static TFET logic designs) enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade-off in operating frequency and power consumption.

As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability-related variability) is an emerging concern that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects. The properties of gate oxide defects are discussed. It is further shown how in particular the electrical properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits.

Metal gate/high-k stacks are in CMOS manufacturing since the 45 nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.

This paper presents a single event upset (SEU) resilient, single event transient (SET) filterable and cost effective latch (referred to as RFEL) using 45 nm CMOS commercial technology. By means of triple mutual feedback CMOS structures, one of which is an input-split Schmitt trigger, and two of which are Muller C-elements, the internal nodes and output node of the latch are self-recoverable from single event upset regardless of the energy of a striking particle. The latch filters a much wider spectrum of single event transient on account of hysteresis property of the embedded input-split Schmitt trigger, and temporal redundancy in the grouped inputs of the Muller C-element at output stage. The latch performs with lower overheads regarding area, power, and delay than most of the single event upset and single event transient simultaneously tolerated latches as well. Simulation results show that the area-power-delay-pulse product of the latch is 65.58% saving on average, and Monte Carlo simulation results demonstrate the equivalent or even less sensitivity of the latch to process, and temperature variations, compared with the previous radiation hardened latches.

One of the major challenges in the design of compact microwave structures is the necessity of simultaneous handling of several objectives and the fact that expensive electromagnetic (EM) analysis is required for their reliable evaluation. Design of multi-band circuits where performance requirements are to be satisfied for several frequencies at the same time is even more difficult. In this work, a computationally efficient design of dual-band microstrip couplers is demonstrated by means of an adaptive response scaling (ARS) technique. ARS is a surrogate-assisted method that exploits a fast surrogate of the high-fidelity EM-simulation model of the coupler at hand constructed from its corrected equivalent circuit. ARS identifies nonlinear frequency and amplitude response scaling that accommodates the misalignment between the low- and high-fidelity models. Due to exploiting the knowledge embedded in the low-fidelity model ARS surrogate exhibits excellent generalisation capability. It is demonstrated here by optimisation of a dual-band microstrip coupler with enhanced bandwidth, working at 1 GHz and 2 GHz frequencies. The optimised design has been obtained at the cost of just a few high-fidelity EM simulations of the structure. Numerical comparisons indicate superiority of ARS over competitive surrogate-assisted techniques. Experimental validation is also provided.

In this study, electrical constant stress method which is one of accelerated tests is applied to power vertical double diffused MOSFETs continued up to 6 hours. The stress induced changes of characteristic parameters (threshold voltage, mobility, etc.) of power MOSFETs are extracted. A resistive load NMOS inverter is set up and degraded power MOSFET effects on its static parameters are investigated experimentally. Besides the obtained experimental results, a simple circuit model is proposed to simulate the stress induced changes in NMOS inverter static parameters. In this manner, obtained experimental results are supported by simulation study. Proposed degradation model has ability to help designers to predict circuit reliability in the early stages of design.

In this work, a method to determine critical circuit blocks for electromigration in an integrated circuit based on a temperature analysis of the metallization layers is developed. Considering a given maximum resistance increase due to the electromigration, a maximum temperature of operation of the interconnects is obtained. By comparing this maximum temperature with the actual operating temperature of the interconnects, which is calculated from the power dissipated by the circuit, the number of critical interconnects and the critical circuit blocks are determined. In this way, the method allows to design the chip floorplanning taking into account the temperature effects in the resistance increase of the interconnects due to electromigration. This helps to reduce the operating temperature of the interconnects, which also reduces the probability of the blocks to fail, improving the circuit reliability.

Methods to estimate circuit reliability are important, especially when nanometer scale technologies are involved. In the present work, two methods, PTM and SPR, are applied to evaluate 9 combinational circuits. The study focuses on determining the limits of PTM and SPR in terms of number of operations, processing time and accuracy. The work explores too the SPR Multi-pass approach, to evaluate the influence of reconvergent signals in circuit's reliability.

An assessment on magnetic tunnel junction (MTJ)/CMOS hybrid circuit reliability is given from the designers point of view, with an advanced fully depleted silicon-on-insulator (FD-SOI) and bulk CMOS. Selected nonvolatile circuit blocks are investigated with respect to power efficiency, sensing latency, process variation and aging degradation. By integrating physical models of reliability issues, related CMOS aging behavior and MTJ compact model are compatibly simulated. The performance fluctuations and degradations of hybrid MRAM circuits are estimated. Simulation results reveal that MRAM-on-FDSOI structure with reliability knobs show improved energy efficiency comparing to MRAM-on-bulk CMOS. The proposed circuit-level design strategies are effective to enhance the performance especially for MRAM-FDSOI integration, which can alleviate process variation and aging induced failure probability.

With nowadays nanometer-CMOS technologies, time-zero and time dependent variability effects (like BTI, CHI, RTN, TDDB, EM, etc) have turned into an even more serious threat to the desired performance of analog and digital integrated circuits. Statistical characterization and modelling of these variability effects entail large testing times, which are typically prohibitive, and huge amounts of data, which are complex to post process. This paper describes novel characterization techniques that overcome these limitations, that is, they are capable of statistically testing nanometer CMOS devices with much shorter completion times. To properly handle the massive amounts of data from characterization, new extraction methods, described in this paper as well, have been developed. With these methods, an accurate variability-aware device model is completed, which can subsequently be used in reliability-aware circuit design methodologies.

In current CMOS advanced technology nodes, accurate extraction of transistor parameters affected by time-dependent variability, like threshold voltage (Vth) and mobility (μ), has become a critical issue for both analog and digital circuit simulation. In this work, a precise VTH0 and U0 BSIM parameters extraction methodology is presented, together with a straightforward IDS to VTH0 shift conversion, to allow the complete study of device aging effects for reliability circuit simulation.