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In Nanosheet (NS) device architecture, it is much more challenging than FinFET to develop a suitable multiple threshold voltage (multi-Vt) integration with more restrictive requirement on the dimensions due to the critical dimension scaling and complex structure. In this abstract, we reported an innovative integration scheme to enable volumeless multi-Vt and metal multi-Vt to provide the multi-Vt solutions in NS technology for high performance computing (HPC) and low-power applications. We developed a new volumeless multi-Vt for NS to solve the device geometry constraint and offer more margin and the opportunity for further sheet-to-sheet spacing (Tsus) reduction. Furthermore, metal gate boundary control (MGBC) was developed to enable variable NS widths on the same wafer to satisfy both HPC and low-power applications.

This paper analyzes and compares three different types of detectors, including CMOS power detectors, bipolar power detectors, and super-regenerative detectors, deployed in the literature for integrated microwave/mm-wave imaging systems in mainstream silicon technologies. Each detector has unique working mechanism and demonstrates different behavior with respects to bias conditions, input signal power, as well as bandwidth responses. Two Figure-of-Merits for both wideband and narrowband imaging have been defined to quantify the detector performance comparison. CMOS and Bipolar detectors are good for passive imaging, while super regenerative detectors are superior for active imaging. The analytical results have been verified by both simulation and measurement results. These analyses intend to provide design insights and guidance for integrated microwave/mm-wave imaging power detectors.

A high-speed, track-and-hold amplifier and interleaved CMOS sample-and-hold circuit are implemented in an InP-on-CMOS fabrication process. Conventional 50- $\Omega $ interchip interconnects between III-V and CMOS circuits are eliminated with heterogeneous integration of III-V on CMOS, yielding higher performance circuits at lower power consumption. The track-and-hold amplifier is based on a double-switching feedback architecture using 250 nm InP HBTs and achieves an IIP3 of 19 dBm at a sampling rate of 30 GS/s. To the author's knowledge, this is the first published result of a high-speed track-and-hold amplifier in an InP BiCMOS process and the first implementation of a feedback linearized track-and-hold at a sampling rate above 2 GS/s. Additionally, a novel HBT buffer with feedback is demonstrated to offer high linearity and low power for driving time-interleaved CMOS sample-and-hold circuits. A 90 nm time-interleaved CMOS sample-and-hold circuit is demonstrated to achieve better than $-$ 53 dBc ${\rm HD}_3$ at a sampling rate of 5 GS/s while consuming roughly 24 mW per channel.

For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm and beyond. Our study suggests promise of this last scheme to meet requirements in line R and EM reliability.

Co/Cu composite interconnect systems were studied. Since wide Cu lines require a diffusion barrier which is simultaneously applied also to fine Co lines to reduce Co volume fraction, through-Cobalt Self-Formed-Barrier (tCoSFB) was employed to thin down TaN barrier to

InP DHBTs are receiving a great deal of attention for its potential in the yet, undefined, 5G systems. In this paper, "waterfall" curves are evaluated for InP DHBTs at 900MHz and show that it can provide an improvement in PAE at low voltages (10% better than GaAs or SiGe HBTs). RF Knee MAG/MSG metrics at 5.4GHz and 15.4 GHz as compared to GaAs HBTs were also measured. These measurements indicate in some bias regions, InP can provide a large advantage in RF Gain compared to GaAs. These results demonstrate that InP DHBTs have significant potential for envelope tracking (ET) and average power tracking (APT) at conventional frequencies (

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

The noise performance of an InP BiCMOS process is presented. The process builds on IBM 90-nm RF CMOS and features heterogeneously integrated 250-nm InP DHBTs with f t /fmax values of ~300 GHz. Noise models have been extracted and the predicted performance agrees well with measurement. The results indicate that this technology is an excellent option for future millimeter-wave low-noise applications.

FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ∼8% performance improvement in the RO delay with reliability meeting the technology requirement [4]. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.

Numerous research groups are currently developing high-performance InP HBTs with fT and fMAX greater than 400 GHz. However, the heavily degenerate doping concentrations used in these devices present new challenges to numerical device simulation. This work focuses on three physical phenomena in InP and In0.53Ga0.47As and their implementation in physics based device simulators. First, the use of the parabolic band approximation yields a constant DOS effective mass, but this results in an erroneously deep Fermi-level under heavily degenerate donor concentrations. An empirical model is presented and shown to have good agreement with previously published simulations and experimental data. Second, bandgap narrowing parameters and a table based model are used as a more generic model for compound semiconductors. Third, calculated parameters to address the Mott transition are used to obtain the proper freecarrier concentrations throughout the HBT. The improper calibration or neglect of these three physical phenomena is shown to alter HBT band profiles at thermal equilibrium by as much as 400 meV; the turn-on voltage by approximately 50 mV; and the fT dependence on JC by approximately 18%. � 2006 Elsevier Ltd. All rights reserved.

High-speed track-and-hold amplifier (THA) circuits are critical for high-speed, high-resolution data converters, particularly in emerging 100Gb/s optical communication systems. High-speed CMOS analog-to-digital converters (ADCs) have been demonstrated to 56GS/s, but the linearity tends to rapidly degrade at high frequency. The use of a high-speed THA can broaden the frequency response, improve the distortion performance, and mitigate some of the timing requirements for high-speed time-interleaved ADCs. Recent THA work has leveraged high-fmax Indium Phosphide (InP) HBTs to implement 50GS/s track-and-hold amplifiers. Nonetheless, a two-chip solution consisting of an InP THA and time-interleaved CMOS ADCs is extremely difficult to package while retaining high-speed performance.

HRL Laboratories is part of an intense research and development effort to leverage the enormously advanced infrastructure of Si CMOS and the high performance of diverse electronic and photonic devices in an integrated technology. While System in a Package (SiP) and System on a Chip (SoC) approaches involve chips produced in their native foundries and subsequent integration using hybridization or multi-chip modules, HRL has pioneered approaches where partially completed wafers of diverse technologies are integrated using highly intimate placement and heterogeneous interconnects to enable transistor-level integration. Novel ICs have been produced in InP BiCMOS and CMOS memristor-integrated technologies. Unprecedented design flexibility is being enabled with intimate integration of GaN HEMTs together with InP and CMOS.

Strain engineering has been in the heart of CMOS technology for over a decade. However, the effectiveness of conventional strain elements, such as stress liners, embedded S/D stressors, and stress memorization, is significantly reduced when device gate pitch is scaled below 100 nm as needed for 14nm node and beyond. Substrate strain engineering, where the channel itself is formed out of a strained semiconductor, e.g. in the form of strained silicon directly on insulator (SSDOI) or strained SiGe-on-insulator has the advantage that the strain is independent of the device pitch or gate length as long as the active region is made sufficiently long and the strain is maintained throughout the device processing. We have already shown that in a FinFET structure the starting biaxial strain in the SSDOI substrate is converted to a more beneficial uniaxial strain, strain can be maintained throughout typical thermal processing, and demonstrated roughly 15% increase in NFET performance in deeply scaled FinFETs. However, this is still far less than the performance gain we reported recently in ETSOI devices. In this work, for the first time we report NFET performance gain in SSDOI FinFETs fabricated with contacted gate pitch (CGP) down to 64nm.

InP HBT technologies have reached a level of maturity where mixed-signal ICs with 1000s of transistors have become fairly routine in a regime where high speed, low jitter, and high dynamic range are discriminators, necessitating simulator-efficient compact model representations covering a range of device sizes and all operating modes. In comparison to the more traditional graded-base SiGe bipolar devices, InP HBTs have a number of traits that make them unique from a modeling perspective. An overview of InP HBT device characteristics is presented, along with highlights of a comprehensive device characterization and modeling strategy implemented to support the development of a scalable compact model based on VBIC for the design of high-speed mixed-signal circuits.

A 2:16 DEMUX IC with clock phase adjustment has been successfully designed, fabricated, and tested as an interfacing component in 30 Gbps and higher transmission systems using HRL's 0.25 μm low power InP DHBT technology with f t of 400 GHz. The novel clock phase adjustment circuit described here allows multiple DEMUXs to be automatically synchronized eliminating the need of complex clock recovery circuits. The IC uses 1460 DHBTs and consumes only 1.85 W of power demonstrating the feasibility of InP DHBTs in low power and large integration ICs.

High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/µm and 1.25mA/µm, and I eff of 0.95mA/µm and 0.70mA/µm at I off =100nA/µm and V DD of 1V, for NFET and PFET, respectively.

Digital Analog converters using InP HBTs and 90nm CMOS have been designed using the novel HRL integration process developed under the DARPA COSMOS program. These circuits demonstrate that this process is capable of providing a compelling alternative to traditional Si/SiGe BiCMOS implementations for producing highly integrated state-of-the-art mixed signal and digitally-assisted analog circuits.

For nFET, mechanism of stress memorization technique (SMT) has been investigated. It showed, for the first time, that SMT effect on nFET improvement is not only from poly gate, but also from Si at extension area. For pFET, a novel low cost technique to improve device performance by enhanced stress proximity technique (eSPT) with Recessed SD (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. 15% improvement in ring delay has been demonstrated with optimized eSPT.

Differential amplifiers incorporating the advantages of both Si and III-V technologies have been fabricated in a wafer scale, heterogeneously integrated, process using both 250 nm InP DHBTs and 130 nm CMOS. These ICs demonstrated gain- bandwidth product of 40-130 GHz and low frequency gain >45 dB. The use of InP DHBTs supports a 6.9 V differential output swing and a slew rate >4times104 V/mus to be achieved with as low as 40 mW dissipated power. A novel on-chip buffer circuit is used to facilitate the on-wafer characterization of these amplifiers. To the authors' knowledge, this is the first demonstration of a high performance IC building block in a heterogeneously integrated process technology.

We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (Csub) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced Ieff and ~15% improved Idlin against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the stress memory technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects strain transfer.

A novel low cost technique to improve device performance by enhanced stress proximity technique (eSPT) with recessed S/D (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. pFET performance with Ion of 520 uA/um at Ioff of InA/um was achieved with the low cost processes. With optimized eSPT, 15% improvement in ring delay has been demonstrated.

When DSB bonding interface falls into highly doped S/D direct silicon bonded (DSB) technology is shown to be scalable regions, there are concerns of high S/D leakage (due to the possible for 32 nm node and beyond for two integration schemes: solid phase defects in the DSB interface) and high S/D resistance due to epitaxy (SPE)-before-shallow trench isolation (STI) and STI-before-SPE. For SPE-before-STI, 32 nm node ground rules can be met by thinning DSB thickness to ~70 nm, which ensures complete removal of boundary defects by STI. For STI-before-SPE, a scaling-independent solution is provided by the use of 45deg rotated (100) base wafers which allow trench-defect-free SPE at the STI edges.

The effects of the integration of two major PFET performance enhancers, embedded SiGe (e-SiGe) junctions and compressively stressed nitride liner (CSL) have been examined systematically. The additive effects of e-SiGe and CSL have been demonstrated, enabling high performance PFET (drive current of 640 muA/mum at 50 nA/mum off state current at 1V) with only modest Ge incorporation (~20 at. %) in S/D. And for the first time, we have demonstrated that by integrating e-SiGe and laser anneal (LA), defect-free e-SiGe can be fabricated, and the benefits of both techniques can be retained. Our study of geometric effects also reveals that e-SiGe can be extended to 45 nm technology and beyond

Two integration schemes for hybrid crystal orientation technology using direct silicon bonded (DSB) substrates and solid phase epitaxay (SPE) processes have been implemented. The shallow-trench-isolation (STI) before SPE approach suffers from trench-edge defects formed at STI edges, which causes high leakage current. The SPE-before-STI approach allows removal of edge defects of SPE by STI. SRAM in 65nm node and eDRAM in 90nm node have been demonstrated on DSB using the SPE-before-STI scheme.

Device performance has been boosted by integrating dual-stress-liners (DSL) in a 45nm low power platform as a cost effective approach. A stress-proximity-technique (SPT) has been explored to improve device performance without adding process complexity. Record drain currents of 840/490 muA/mum have been achieved for NMOS and PMOS, respectively, at 1.2V and off-leakage current of 1nA/mum. Junction profiles have been optimized to reduce the gate-induced-drain-leakage (GIDL). An asymmetric IO has been integrated into this low power technology for the first time, offering multiple advantages including low cost, performance gain up to 30% and reliability improvement as well

Recent developments in highly scaled SiGe and InP IC technologies have yielded devices with f/sub T/ and f/sub max/ figures-of-merit well beyond 300GHz, bringing with them the potential to operate circuits of considerable complexity at clock rates exceeding 100GHz. An initial emphasis upon digital applications helps to put the technologies on a roadmap where further development can be fueled to open the door to other mixed-signal possibilities. Designing circuits at these frequencies requires a balance of thermal and electromagnetic concerns along with the traditional IC design issues, but measured results are demonstrating that these concerns are manageable.

We present a systematic study on maximizing polysilicon gate activation for aggressively scaled 0.1 /spl mu/m CMOS technologies. The fundamental limit of gate activation due to poly depletion effect was investigated in terms of gate implant/anneal condition and sequence, poly grain size, dopant penetration and activation. For the first time, we achieved significant improvement in CMOS performance by developing a novel process of "gate postdoping" to decouple implant and anneals for gate, source/drain, and extension. The method successfully reduces the poly depletion effect and thus the equivalent gate oxide thickness in inversion by up to /spl sim/2 /spl Aring/, improving CMOS on-currents by 9/spl sim/33% over a conventional process.