Search

The surface-potential-based compact MOS model PSP is reviewed with special emphasis to features of interest to analog and RF designers. Various aspects of the model are discussed, such as Gummel symmetry, capacitance reciprocity at V DS = 0 V, parasitic resistances, junction modeling, distortion modeling, and noise modeling. Examples from circuit design are used to illustrate the benefits of the PSP model.

A computationally efficient physics-based wideband predictive inductor compact model is presented that is capable of evaluating the impact on inductance and quality factor of dummy metal fill-cells. In a modern integrated-circuit process, high amounts of these fill-cells are required to meet metal density rules and guarantee adjacent circuit integrity. The predictions made with this model are shown to be in agreement with data measured on symmetrical octagonal inductors realized in a 90-nm CMOS process with varying amounts of dummy metal fill-cells. We further provide all inductance equations, list additional sources of eddy current losses, and discuss layout modifications, which would further improve the performance of the integrated inductors

For the first time, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed. Based on measurements and physical device simulations we quantify the increasing danger of poly gate depletion with downscaling on the RF noise parameters of CMOS devices. While poly depletion does not affect the minimum noise figure, it results in a degradation of the noise matching freedom for RFIC designers. This trend worsens with technology downscaling.

A new approach to numerical noise simulation for MOSFETs based on bipolar 2D drift-diffusion and hydrodynamic models is presented, where the hierarchical approach for volume transport has been extended to the case of inversion layers. With the new models RF noise in scaled NMOSFETs is investigated and simulation results are compared to measurements for a 180 nm technology. Important noise quantities like the drain and gate excess noise factors and the gate/drain correlation coefficient are discussed in detail. It is found that the drain excess noise factor increases only moderately in short channel devices down to 70 nm gate length independent of the device type (bulk, SOI or double gate). Although the gate excess noise factor increases significantly at shorter gate lengths, the minimum noise figure strongly decreases predicting superior noise performance for sub-100 nm devices. Furthermore, the impact of the substrate resistance on RF noise is discussed including bias conditions near breakdown, where carrier generation by impact ionization becomes significant.

A new noise-figure measurement method, which combines the simplicity of the "classical" Y-factor method with the accuracy of the widely used "cold noise-source" method, is reported. Implemented in our fully automated wide-band 1-18-GHz on-wafer noise-parameter measurement system, accurate results are obtained using a small set of precharacterized source impedances. We illustrate our method and its accuracy with data taken on a low-noise GaAs pseudomorphic high electron-mobility transistor device, and quantify the impact of the instrumental uncertainties on the extracted noise parameters.

The impedance errors remaining after applying the industry standard "open-short," a "pad-open-short," and a "open-short-load" deembedding scheme on a 0.43-nH 20-GHz high-Q single-loop inductor test structure are investigated using real S-parameter data taken up to 50 GHz. Since the latter two deembedding schemes both correct for all parasitic elements of the test structures, they are, at least in principle, error free. The accuracy of the "open-short-load" deembedding scheme, however, critically depends on how well the reactive part of the load resistance is accounted for. This issue makes the more simple "pad-open-short" deembedding scheme an attractive choice because the required split between external and internal capacitances is easy to make, either based on process and layout information or from measurements done on a "pad" dummy structure

The impedance errors remaining after conventional de-embedding for a high-speed transistor and a single-loop inductor test structure are investigated. A new de-embedding strategy using a physics-based lumped-element model for the test-structure parasitics calibrated on the frequency-dependent "open" and "short" dummy impedances is described, which reduces the experimental uncertainty on the de-embedded figures of merit. Using this new "calibrated lumped-element" de-embedding technique, we have been able to increase the "worst-case" values for the quality factor Q of a 0.6-nH 10-GHz single-loop inductor from 15 to 20 and for the f/sub max/ of a high-speed SiGe bipolar transistor from 80 to 110 GHz. The de-embedding technique presented here is of great importance to develop confidence in on-wafer S-parameter measurements taken at ever increasing microwave frequencies.

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

This paper presents an 8-elements phased array receiver front-end in 45nm CMOS technology. The receiver uses a 4-bit resolution RF phase shifter to compensate for the free-space propagation delay and an active eight-to-one power combiner enabling beam-forming. Each path shows more than 15.8dB of power gain with

A new, compact expression for the effective FinFET gate resistance is derived and validated on experimental data. Moreover, FinFET thermal noise measurements are presented and analyzed. We show that the observed increase of drain current noise with drain-source voltage is not due to microscopic excess noise, but to the access resistances, which modify the transfer of channel thermal noise to the terminals.

First the surface-potential-based compact MOS model, PSP, is introduced. After a discussion of the general advantages of this model, it is benchmarked against measurements from the 45 nm technology node. Finally, we zoom in on the modeling in PSP of two effects that are of special importance for RF applications: distortion and noise.

Compact modeling is an area that gets more and more mature. Collaborations and standardization efforts have emerged. In this paper we present some special requirements that are important when constructing physics-based compact models. We will substantiate our statements on two recent examples, an inductor model and a MOSFET model.

The physical background of the thermal noise equations of the PSP MOSFET model [1] is presented. The PSP thermal noise model is shown to pass a number of proposed benchmark tests for MOSFET thermal noise. Without any fitting parameters, it is shown to predict with great accuracy a collection of experimental data on three modern CMOS technologies. The impact of device layout on noise properties is discussed and demonstrated experimentally.

A highly accurate predictive inductor model for integrated symmetric inductors with center tap and patterned ground shield is presented. This model is based on a modified Greenhouse algorithm where current crowding due to skin and proximity effects is included by considering the spread in parallel sub-loop inductances. This scalable symmetrical inductor equivalent circuit model covers all operating conditions, and yet only requires dimensions and back-end layer thicknesses. We have verified this scalable model for a large number of inductors from three industrial IC processes and found excellent agreement with measured inductances, Q-factors, and resonance frequencies.

Accurate compact modeling of induced gate noise is a prerequisite for RF CMOS circuit design. Existing models underestimate the induced gate noise for short-channel devices. In this paper, a new model is introduced, based on an improved Klaassen-Prins approach, which accurately accounts for velocity saturation. The model accurately describes noise without fitting any additional parameters.

We demonstrate that the quality factors measured on on-wafer (spiral) inductor test-structures are largely influenced by the choice between ground-signal and ground-signal-ground probe configuration. In particular when the SOLT network analyzer calibration technique is used in combination with ground-signal probing, the quality factor value can be overestimated significantly.

We study the the thermal noise of short-channel NMOS transistors in a commercially available 0.13 micron CMOS technology. The experimental results are modeled with a non-quasi-static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parmeters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In our optimized device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance.

We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

A large-signal non-quasi-static (NQS) model for RF CMOS circuit simulation is presented that can be built from channel segments described by conventional QS models like BSIM3 or MOS Model 9. This large-signal NQS model is shown to give a very accurate prediction of the high-frequency behaviour of the intrinsic transconductance, the power gain and input resistance.

High-Q spiral inductors, either realized as discrete elements in thin-film technologies, or as integrated components in IC processes, are essential to realize key RF circuitry like VCO's and LNA's. We have demonstrated for the first time that by dividing a spiral inductor into four parallel current paths of equal resistance and inductance current crowding can be suppressed, allowing a record Q of 15 for a 2 GHz 5 nH inductor in standard CMOS, representing a 40 % improvement over previous art. The proposed division into parallel current paths can be realized without process modifications, reduces CMP dishing, and is expected to provide even larger performance gains in terms of quality factor Q and inductor area for IC and thin-film processes employing thicker metal layers and low-K materials.

In this paper we present a compact physically based charge model, which describes accurately the unique features of the SOI LDMOS. The model uses a modified Ward and Dutton partitioning scheme to account for the lateral doping gradient in the channel region and the overlap of the front gate over the drift region. The model has been implemented in SPICE3f5 and capacitance measurements are shown to agree well with the simulations.

The distortion behaviour of MOSFETs is important for RF-applications. In this paper the influence of technology variations (oxide thickness, substrate doping,...) on distortion is investigated using measurements and a recently developed compact MOSFET model. The influence on distortion of technology scaling down to 0.18 /spl mu/m is verified and further scaling according to the ITRS-roadmap is predicted.

An off-state S-parameter technique characterizes the NPN substrate resistance-capacitance network. The results are useful in designing RF test structures, modeling substrate effects for circuit simulation, and characterizing perimeter and area capacitance components from a single device.

Modem CMOS technologies are becoming increasingly attractive for RF applications.This imposes stringent requirements on compact models used in circuit simulation: not only currents and charges, but also noise, power gain, impedances, and harmonic distortion must be modelled accurately. In this paper several of these issues will be addressed with the help of Philips’ new public-domain compact MOS model, MOS Model 11.

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1 noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

RF application of CMOS requires accurate modelling of transistor properties, such as impedance levels, power gain, noise, distortion, substrate parasitics and nonquasi-static effects. Apart from noise, until now relative little attention has been paid to these properties in compact models for circuit simulation. Here clear experimental results will be used to illustrate the accuracy and limitations of state-of-the-art compact models. Wherever possible, improvements or macro models that can be used for circuit simulation will be presented.